EP80579 Datasheet, PDF (1903/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
49.5.20.2 CRU DC Characteristics
Table 49-102.CRU Differential Clock DC Specifications
Symbol
V_IL
V_IH
V_CROSS(abs
)
V_CROSS(rel)
ΔV_CROSS
Parameter
Input Low Voltage
Input High Voltage
Absolute Crossing Point
Relative Crossing Point
Range of Crossing Point
Min
-0.150
0.660
0.250
0.250+0.5(V
HAVg-0.71)
N/A
Typical
0.00
0.710
N/A
N/A
N/A
Max
0.150
0.850
0.550
0.550+0.5(V
HAVg-0.71)
0.140
Units
V
V
V
V
V
Figure
49-47
49-47
Notes
1
1
49-47, 49-48 1, 2, 3, 6, 9
49-47, 49-48
1, 2, 3, 6, 7,
9
49-47, 49-48 1, 2, 8, 9
V_RBM
Ringback Margin
0.200
N/A
N/A
V
49-47
1, 4, 9
V_TM
Threshold Margin
V_CROSS-0.10
N/A
V_CROSS+0.10
V
49-47
1, 5, 9
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Crossing voltage is defined as the instantaneous voltage value when the rising edge of CLKP100 equals the falling edge
of CLKN100.
3.
VHavg is the statistical average of the VH measured by the oscilloscope.
4.
Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the
maximum Falling Edge Ringback.
5.
Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver
switches. It includes input threshold hysteresis.
6.
The crossing point must meet the absolute and relative crossing point specifications simultaneously.
7.
VHavg can be measured directly using "Vtop" on Agilent* scopes and "High" on Tektronix* scopes.
8.
ΔV_CROSS is defined as the total variation of all crossing voltages as defined in note 2.
9.
Guaranteed by design. These values are typical values seen for this process, but not measured during production
testing.
Figure 49-47.CRU Differential Clock Waveform
CLKN100
Threshold
Region
CLKP100
Tph
Crossing
Voltage
Crossing
Voltage
Tpl
Tp
Ringback
Margin
Overshoot
VH
Rising
Edge
Ringback
Falling
Edge
Ringback
VL
Undershoot
Tp = T1: CLK100 period
T2: CLK100 period stability (not shown)
Tph = T3: CLK100 pulse high time
Tpl = T4: CLK100 pulse low time
B4965-01
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1903