EP80579 Datasheet, PDF (149/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 5-11 summarizes the capabilities of the PCI-Express error handling for each of
the features that the unit is expected to provide.
Table 5-11. Summary of IMCH PCI-Express Error Reporting Capabilities
Feature
Implementation
Enabling and
Masking Error
Reporting
The UNCERRMSK, UNCEDMASK, CORERRMSK, COREDMASK, RPMERRSTS, PEAMASKERR,
RPERRCMD, and PEAERRDOCMD registers enables and masks error reporting.
The PCICMD register also enables and masks SERR signals.
Logging Details
PCI Express* controllers captures error logging information in the following registers:
• RPMERRSTS errors: ERRSID captures requester IDs.
• Errors with Header Capture: HDRLOG0, HDRLOG1, HDRLOG2, and HDRLOG3 captures
the first four 32-bit words of the headers.
This information is in addition to the status information in UNCERRSTS, CORERRSTS,
RPMERRSTS, PEAFERR, and PEANERR.
Reporting Multiple The PEANERR and RPERRMSTS registers captures “next” errors. This register indicates up
Errors
to one additional error (beyond the first error) of each type.
Data Poisoning PCI Express* controllers pass along error information to poison data.
See Section 16.4, “PCI Express* Port A Standard and Enhanced Registers: Bus 0,
Devices 2 and 3, Function 0” for additional details.
For additional discussion on the IMCH responses to transactions from the PCI Express*
ports, see Section 10.1, “Overview”.
5.4
5.4.1
Error Reporting by the IICH
The EP80579 IICH devices rely on the PCI error reporting architecture to reporting
errors. In this architecture, details on the errors are logged in the PCI status register
from the per-device PCI configuration header. A parity or other severe system error
causes the device to generate an IA SERR signal.
Errors that occur on the NSI bus between the IMCH and IICH report through the
NSI_FERR and NSI_NERR infrastructure as Section 5.3.1, “Overview of the First and
Next Error Architecture” on page 141 and Section 5.3.6, “Unit-Level Errors from the
NSI” on page 145 describe.
On the IICH backbone, IICH devices must rely entirely on the SERR signal that the
device generates on an error event to report the error. The IICH does not provide any
other capability (such as data poisoning) that would allow a consumer of IICH data to
note an error. As a result, an IICH device can return erroneous data on a request.
The remainder of this section describes the error handling capabilities of the units in
the IICH.
SMBus Interface
The IICH provides a SMBus controller that can generate an interrupt or SMI on error
events and can also use the PCI SERR infrastructure to report errors. The HCFG register
selects either SMI or interrupt signaling; parity and system errors always signal
through SERR. Table 5-12 summarizes the error conditions that the controller reports.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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