EP80579 Datasheet, PDF (908/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
24.3.1.2
Note:
Offset 02h: HCTL: Host Control Register
A read to this register clears the pointer in the 32-byte buffer.
Table 24-20. Offset 02h: HCTL: Host Control Register (Sheet 1 of 4)
Description:
View: PCI
BAR: SM_BASE (IO)
Bus:Device:Function: 0:31:3
Offset Start: 02h
Offset End: 02h
Size: 8 bit
Default: 00h
Power Well: Resume
Bit Range
07
06
Bit Acronym
Bit Description
Sticky
PEC_EN
START
Packet Error Check Enable:
0 = SMBus host controller does not perform the
transaction with the PEC phase appended.
1 = Causes the host controller to perform the SMBus
transaction with the Packet Error Checking phase
appended. For writes, the value of the PEC byte is
transferred from the PEC Register. For reads, the
PEC byte is loaded in to the PEC Register. This bit
must be written prior to the write in which the start
bit is set.
0 = This bit will always return 0 on reads. The
HOST_BUSY bit in the Host Status register (offset
00h) can be used to identify when the command is
finished.
1 = Writing a 1 to this bit initiates the command
described in the SMB_CMD field. All registers
should be setup prior to writing a 1 to this bit
position.
Bit Reset
Value
0h
0h
Bit Access
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
908
August 2009
Order Number: 320066-003US