EP80579 Datasheet, PDF (1579/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 39-1. CiA Recommended bit rate and timing Parameters (Sheet 2 of 2)
Bit Rate
(kbits/s)
10
Bus
Length
(m)
5000
Nominal
Bit Time
tb (us)
Number of
Time Quanta
per Bit
Length of
Time
Quantum Tq
(us)
Location
of Sample
Point wrt
tq
Location
of Sample
Point (us)
Comments
100
16
6.25
14 Tq
87.5
Sampling Mode = Single
Synchronization Mode = Reccessive to dominant edges only
Synchronization Jump Width = 1 * Tq
Phase Segment 2 = 2 * Tq
Minimum bit rate
The CiA recommended timing parameters for each bit rate is show in Figure 39-7.
39.4.4.2 Setting Proper Bit Rate, tseg1 and tseg2
The CAN controller unit provides the following programmable timing parameters, which
can be used to achieve CiA recommended bit rates:
• cfg_tseg1 (Propagation Delay Segment + Phase Buffer Segment 1): This is used to
compensate for edge phase errors but also consists of a propagation segment,
which is used to compensate for signal delays in the network.
• cfg_tseg2 (Phase Buffer Segment 2): This is also used for compensation of edge
phase errors.
• cfg_sjw (Synchronization Jump Width): This defines how far the re-synchronization
may move the sample point inside the limits defined by the phase buffer segments
to compensate for edge phase errors.
As shown in Figure 39-7, the sample point separates tseg1 and tseg 2, this is the point
in time where the bus level is read and interpreted.
Figure 39-7. Bit Rate and Time Settings
bit time
1
tseg1 + 1
tseg2 + 1
time quanta (TQ)
Sample Point
bittime = ( 1 + ( tseg1 + 1 ) + ( tseg2 + 1 ) ) * timequanta
timequanta= ^{bitrate + 1}
f_clk
The CAN unit in the EP80579 operates at a frequency of 40Mhz. Based on this
frequency, the recommended timing parameter values are as show in Table 39-2.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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