EP80579 Datasheet, PDF (1055/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
27.3.3
Note:
General Power Management I/O-Mapped Registers
Table 27-10 shows the registers associated with ACPI and Legacy power management
support. These registers are enabled in the PCI Device 31: Function 0 space (ACPI
Enable in Section 19.2.2), and can be moved to any I/O location (128-byte aligned)
determined by ABASE in Section 19.2.2.1 (referenced in this chapter by PMBASE). The
registers are defined to be compliant with the Advanced Configuration and Power
Interface (ACPI) Specification, Rev. 2.0, and generally use the same bit names. All
reserved bits and registers will always return 0 when read, and will have no effect when
written.
For more information on the format of the register description tables that follow in this
chapter, see Section 7.1.1, “Register Description Tables” on page 183).
Table 27-10. Bus 0, Device 31, Function 0: Summary of LPC Interface Power Management
General Configuration Registers Mapped Through PMBASE I/O BAR
Offset Start Offset End
Register ID - Description
Default
Value
00h
02h
04h
08h
10h
14h
28h
2Ch
30h
34h
38h
3Ah
44h
00h
02h
04h
B8h
10h
14h
28h
2Ch
30h
34h
38h
3Ah
44h
“Offset 00h: PM1_STS – Power Management 1 Status Register” on page 1056
0000h
“Offset 02h: PM1_EN - Power Management 1 Enables Register” on page 1058
0000h
“Offset 04h: PM1_CNT - Power Management 1 Control Register” on page 1059
0000h
“Offset 08h: PM1_TMR - Power Management 1 Timer Register” on page 1060
00000000h
“Offset 10h: PROC_CNT - Processor Control Register” on page 1060
00000000h
“Offset 14h: LV2 - Level 2 Register” on page 1063
00h
“Offset 28h: GPE0_STS - General Purpose Event 0 Status Register” on page 1063 00000000h
“Offset 2Ch: PMBASE_GPE0_EN - General Purpose Event 0 Enables Register” on
page 1067
00000000h
“Offset 30h: SMI_EN - SMI Control and Enable Register” on page 1068
00000000h
“Offset 34h: SMI_STS - SMI Status Register” on page 1071
00000000h
“Offset 38h: ALT_GPI_SMI_EN - Alternate GPI SMI Enable Register” on page 1073 0000h
“Offset 3Ah: ALT_GPI_SMI_STS - Alternate GPI SMI Status Register” on page 1074 0000h
“Offset 44h: DEVTRAP_STS - DEVTRAP_STS Register” on page 1074
0000h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1055