EP80579 Datasheet, PDF (562/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-188.Offset 70h: PEA1LNKCAP - PCI Express Link Capabilities Register (Sheet 2 of
2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 70h
Offset End: 73h
Size: 32 bit
Default: 0303E441h
Power Well: Core
Bit Range
11 : 10
09 : 04
03 : 00
Bit Acronym
Bit Description
Sticky
Reserved
MLW
MLS
Reserved
Maximum Link Width: This field indicates the maximum
width of the PCI Express* link. Device 3 reports a value of
000100b indicating a maximum link width of x4.
All other encodings are reserved.
Maximum Link Speed:
0001b 2.5 Gb/s supported
All other settings are reserved.
Bit Reset
Value
01b
000100b
0001b
Bit Access
RO
RO
16.4.1.50 Offset 74h: PEALNKCTL - PCI Express* Link Control Register
This register controls PCI Express* link specific parameters.
Table 16-189.Offset 74h: PEALNKCTL - PCI Express Link Control Register (Sheet 1 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 74h
Offset End: 75h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 74h
Offset End: 75h
Size: 16 bit
Default: 0001h
Power Well: Core
Bit Range
15 : 08
07
06
Bit Acronym
Bit Description
Sticky
Reserved
ES
CCC
Reserved
Extended Synch: Provides external devices monitoring
the link with additional time for to achieve bit and symbol
lock before the link enters L0 state and resumes
communication.
0 = Normal
1 = Reserved.
Common Clock Configuration:
0 = This component and the component at the opposite
end of the link are operating with asynchronous
reference clocks.
1 = This component and the component at the opposite
end of the link are operating with a distributed
common reference clock.
Bit Reset
Value
00h
0b
0b
Bit Access
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
562
August 2009
Order Number: 320066-003US