EP80579 Datasheet, PDF (1701/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 42-7. EXP_TIMING_CS[1-7] - Expansion Bus Timing Registers (Sheet 2 of 2)
Description: Timing and Control Registers
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:8:0
00000004h
Offset Start: at 4h
Offset End: 00000007h
at 4h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
08
07
06
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Sync_Intel
EXP_CHIP
BYTE_RD16
HRDY_POL
MUX_EN
SPLT_EN
Reserved
WR_EN
BYTE_EN
Synchronous Intel StrataFlash^® select. This bit must be 0
if CYC_TYPE is not programmed to Intel cycles.
0 = Target device is not a Synchronous Intel StrataFlash
1 = Target device is a Synchronous Intel StrataFlash
0 = Target device is not an EP80579
1 = Target device is an EP80579. This bit must only be set
to 1 when CYC_TYPE is configured to be Intel Cycles and
Sync_Intel is set to 0.
Byte read access to Word device
0 = Byte access disabled.
1 = Byte access enabled.
HPI HRDY polarity (reserved for exp_cs_n[7:4] only)
0 = Polarity low true.
1 = Polarity high true.
0 = Separate address and data buses.
1 = Multiplexed address / data on data bus.
0 = Internal Bus split transfers disabled.
1 = Internal Bus split transfers enabled.
Reserved. This bit must be written with a ‘0’. Writing a ‘1’
will result in unpredictable behavior.
0 = Writes to CS region are disabled.
1 = Writes to CS region are enabled.
0 = Expansion bus uses 16-bit-wide data bus
1 = Expansion bus uses only 8-bit data bus
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
0h
0h
Bit Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
Note:
The seven EXP_TIMING_CS[1-7] registers have following starting offsets:
00000004h - EXP_TIMING_CS1
00000008h - EXP_TIMING_CS2
0000000Ch - EXP_TIMING_CS3
00000010h - EXP_TIMING_CS4
00000014h - EXP_TIMING_CS5
00000018h - EXP_TIMING_CS6
0000001Ch - EXP_TIMING_CS7
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1701