EP80579 Datasheet, PDF (533/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.9
Offset 0Ch: CLS - Cache Line Size Register
This register is normally set by system firmware and OS to the system cache line size.
Table 16-148.Offset 0Ch: CLS - Cache Line Size Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 0Ch
Offset End: 0Ch
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 0Ch
Offset End: 0Ch
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
Cache Line Size: This register is set by BIOS or OS to the
CLS
system cache line size. Implemented as read-write field
only for compatibility reasons. It has no effect on the
device’s functionality.
Bit Reset
Value
00h
Bit Access
RW
16.4.1.10 Offset 0Eh: HDR - Header Type Register
This register identifies the header layout of the configuration space.
Table 16-149.Offset 0Eh: HDR - Header Type Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 0Eh
Offset End: 0Eh
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 0Eh
Offset End: 0Eh
Size: 8 bit
Default: 01h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
HDR
Header Type Register: This value indicates the Header
Type of the device.
01h = single-function device with Bridge layout.
Bit Reset
Value
01h
Bit Access
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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