EP80579 Datasheet, PDF (771/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
20.2.1.6 Offset 87h: DMA_MPL[0-3] - DMA Memory Low Page Registers for
Channels 0-3
Table 20-9. Offset 87h: DMA_MPL[0-3] - DMA Memory Low Page Registers for Channels 0-
3
Ch. 0: 87h - 97h,
Description:
Ch.
Ch.
1:
2:
83h
81h
-
-
93h,
91h,
Ch. 3: 82h,
View: IA F Base Address: 0000h (IO)
Offset
Start:
87h,
81h,
83h,
82h
Offset
End:
97h,
91h,
93h,
82h
Size: 8 bit
Default: XXXXXXX
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky Bit Reset Value Bit Access
DMALP
DMA Low Page (ISA Address bits [23:16]): This
register works in conjunction with the DMA controller's
Current Address Register to define the complete 24-bit
address for the DMA channel. This register remains
static throughout the DMA transfer. Bit 16 of this
register is ignored when in 16 bit I/O count by words
mode as it is replaced by the bit 15 shifted out from the
current address register.
Xh
RW
20.2.1.7 Offset 8Bh: DMA_MPL[5-7] - DMA Memory Low Page Registers for
Channels 5-7
Table 20-10. Offset 8Bh: DMA_MPL[5-7]: DMA Memory Low Page Registers for Channels 5-
7
Ch. 5: 8Bh - 9Bh,
Description: Ch. 6: 89h - 99h,
Ch. 7: 8Ah - 9Ah
View: IA F Base Address: 0000h (IO)
Offset
Start:
8Bh,
8Ah
89h,
Offset
End:
9Bh,
9Ah
99h,
Size: 8 bit
Default: XXXXXXX
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky Bit Reset Value Bit Access
DMALP
DMA Low Page (ISA Address bits [23:16]): This
register works in conjunction with the DMA controller's
Current Address Register to define the complete 24-bit
address for the DMA channel. This register remains
static throughout the DMA transfer. Bit 16 of this
register is ignored when in 16 bit I/O count by words
mode as it is replaced by the bit 15 shifted out from the
current address register.
Xh
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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