EP80579 Datasheet, PDF (955/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 25-21. USBCMD: USB Command Register (Sheet 2 of 2)
Description:
View: PCI
BAR: USBIOBAR (IO)
Bus:Device:Function: 0:29:0
Offset Start: 00h
Offset End: 01h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
03
02
01
00
Bit Acronym
Bit Description
Sticky
EGSM
GRESET
HCRESET
RS
Enter Global Suspend Mode:
0 = Software resets this bit to 0 to come out of Global
Suspend mode. Software writes this bit to 0 at the
same time that Force Global Resume (bit 4) is
written to 0 or after writing bit 4 to 0.
1 = Host Controller enters the Global Suspend mode.
No USB transactions occurs during this time. The
Host Controller is able to receive resume signals
from USB and interrupt the system. Software must
ensure that the Run/Stop bit (bit 0) is cleared prior
to setting this bit.
Global Reset:
0 = This bit is reset by the software after a minimum of
10 ms has elapsed as specified in the Universal
Serial Bus (USB) Specification, Rev. 2.0.
1 = Global Reset. The host controller sends the global
reset signal on the USB and then resets all its
logic. Chip Hardware Reset has the same effect as
Global Reset (bit 2), except that the host controller
does not send the Global Reset on USB.
Host Controller Reset: The HCReset effects on hub
registers are slightly different from Chip Hardware Reset
and Global USB Reset. The HCReset affects bits [8,3:0]
of the Port Status and Control Register (PORTSC) of
each port. HCReset resets the state machines of the
Host Controller including the Connect/Disconnect state
machine (one for each port). When the Connect/
Disconnect state machine is reset, the output that
signals connect/disconnect are negated to 0, effectively
signaling a disconnect, even if a device is attached to
the port. This virtual disconnect causes the port to be
disabled. This disconnect and disabling of the port
causes bit 1 (connect status change) and bit 3 (port
enable/disable change) of the PORTSC to get set. The
disconnect also causes bit 8 of PORTSC to reset. About
64 bit times after HCReset goes to 0, the connect and
low-speed detect will take place and bits 0 and 8 of the
PORTSC will change accordingly.
0 = Reset by the host controller when the reset process
is complete.
1 = Reset. When this bit is set, the host controller
module resets its internal timers, counters, state
machines, etc. to their initial value. Any transaction
currently in progress on USB is immediately
terminated.
Run/Stop:
0 = Stop. Completes the current transaction on the
USB and then halts. The HC Halted bit in the status
register indicates when the Host Controller has
finished the transaction and has entered the
stopped state. The Host Controller clears this bit
when the following fatal errors occur: consistency
check failure, Memory access errors.
1 = Run. Proceeds with execution of the schedule and
continues execution as long as this bit is set.
Bit Reset
Value
0h
0h
0h
0h
Bit Access
RW
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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