EP80579 Datasheet, PDF (97/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 1-3.
Acronym Table
Term
LSB
MCH
MII
MMIO
MMR
MSb
MSB
MSI
MTBF
NCM
NIC
NOS
NSI
OS
OSPM
P2P
PB
PBM
PCI
PCM
PEC
PHY
POC
RASUM
RCBA
RCRB
RDMA
RFL
RGMII
RMII
RMW
RTC
RTCRESET#
RX
SATA
SATA*
Description
Least Significant Byte
Memory Controller Hub, MCH and IMCH are interchangeable for the entire document
Media Independent Interface (16 pins per port)
Memory Mapped I/O
Memory Mapped Register
Most Significant Bit
Most Significant Byte
Message-signaled interrupt that encodes interrupts as an in-band 32-bit write transaction.
Mean Time Between Failures
Non Coherent Memory
Network interface controller
Network Operating System
North South Interface. The designation for the proprietary, internal high-speed serial
interconnect between the IMCH and the IICH.
Operating System.
Operating System directed Power Management
See Peer-to-Peer in Table 1-4
Packet Buffer
Packet Buffer Memory
Peripheral Component Interconnect Local Bus. A 32- or 64-bit bus with multiplexed
address and data lines that is primarily intended for use as an interconnect mechanism
within a system between processor/memory and peripheral components or add-in cards.
Pulse Code Modulation
Packet Error Checking. This is an SMBUS 2.0 feature.
Physical Layer Device
Power-on-configuration
Reliability, Availability, Serviceability, Usability, and Manageability, which are all important
characteristics of servers.
Root Complex Base Address register at D31:F0:RegF0h. It specifies the physical address
of the CMI Configuration Space. Also used in RCBA + offset xxxxh or RCBA + xxxxh
(where xxxxh is the offset) to indicate register location in the CMI Configuration Space.
Root Complex Register Block, as defined in the PCI Express* Specification v1.0a. In the
IICH context, it refers to a part of the CMI Configuration Space (see RCBA, above).
Remote Direct Memory Access
Receive FIFO Level
Reduced GMII
Reduced MII (7 pins per port)
Read-Modify-Write operation
Real-Time Clock
Signal that resets the RTC well (but does not clear the RTC RAM memory contents).
Receive
Serial Advanced Technology Attachment
Serial ATA, an industry specification of the interface for storage controllers and devices.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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