EP80579 Datasheet, PDF (1023/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 26-50. Periodic DMA Engine Memory Reads
qTD
Queue Head
Out Data
13
17
Up to 257
Only the 64-bit addressing format is supported.
Only the 64-bit addressing format is supported.
Large read requests are broken down into smaller aligned read
requests based on the setting of the Read Request Maximum
Length field.
Periodic DMA read policies:
1. The EHC Periodic DMA Engine (PDE) does not generate accesses to main memory
unless all three of the following conditions are met:
a. The HCHalted bit is 0 (memory space, offset 24h, bit 12). Software clears this
bit indirectly by setting the RUN/STOP bit to 1.
b. The Periodic Schedule Status bit is 1 (memory space, offset 24h, bit 14).
Software sets this bit indirectly by setting the Periodic Schedule Enable Bit to 1.
c. The Bus Master Enable bit is 1 (configuration space, offset 04h, bit 2).
2. Once the above conditions are met, the PDE waits until the frame index counter
rolls over from the end of microframe 6 to the beginning of microframe 7 to begin
prefetching for microframe 0 of the next frame. This means the initial memory
access may be delayed up to 1 ms after the DMA-enabled conditions are met.
Further delays within the arbitration and datapath are also possible before the first
read request is presented on the IMCH/IICH link.
3. The Periodic Frame List Entry is always read from memory before any data
structures associated with the new microframe are accessed.
4. Prefetching is limited to the current and next microframes only. If prefetching is
disabled, the periodic DMA engine will perform transactions serially (no pipelining)
and will read structures for the current microframe only.
5. The PDE fetches structures in the periodic list until all information (including data)
is available to run one USB transaction before beginning to fetch the structures for
a pipelined transaction. For High-Bandwidth Out transactions, all of the data may
not fit into the Data FIFO; in those cases, the next pipelined control structure
fetches will be delayed until some data is delivered to USB.
6. The PDE does not refetch the control structure between “Multi” packets of a High
Bandwidth endpoint.
7. The PDE will not generate any control structure reads (including the frame list
index) if both of the transaction buffers are occupied. Data reads are the only read
requests that will be generated by the PDE in this case.
8. The PDE will not pipeline fetch a control structure (iTD, siTD, or QH) if the other
transaction slot contains that control structure already. This is to avoid executing
based on stale fields in the control structure since a status write (or overlay) is
expected to occur following execution of the pending transaction. The PDE will
traverse the schedule (periodic frame list entry and any inactive control structures
for the microframe) before encountering the Link Pointer to the stale structure. At
that point the fetching pauses until the pending transaction is completed. The iTD
could be refetched since a separate status is maintained for each microframe; the
PDE will not attempt this optimization.
9. Once the PDE checks the length of a periodic packet against the remaining time in
the microframe (late-start check) and decides that there is not enough time to run
it on the wire, then the EHC switches over to run asynchronous traffic. The EHC
does not attempt to look for any shorter packets in the remainder of the periodic
schedule that might be able to fit in the current microframe.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1023