EP80579 Datasheet, PDF (1302/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.10.1.22 Offset E8h: SMIA – Signal Target IA Mask Register
Table 35-113.Offset E8h: SMIA: Signal Target IA Mask Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:6:0
Offset Start: E8h
Offset End: E8h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 01
00
Bit Acronym
Bit Description
Sticky
Reserved
SMIA
IA mask bit: If set to 1h, an interrupt is sent to the IA as
either an INTx or MSI based on the PCI signaling
configuration when detect SSP Interrupt
Bit Reset
Value
0h
0h
Bit Access
RW
RW
35.10.1.23 Offset E9h: Reserved Register
Writing to the register will result in undefined behavior.
35.10.1.24 Offset EAh: Reserved Register
Writing to this register will result in undefined behavior.
35.10.1.25 Offset ECh: SINT – Signal Target Raw Interrupt Register
Table 35-114.Offset ECh: SINT: Signal Target Raw Interrupt Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:6:0
Offset Start: ECh
Offset End: ECh
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 01
00
Reserved
SINT
Interrupt: Read-only view of SSP Interrupt
Sticky
Bit Reset
Value
0h
0h
Bit Access
RO
RO
35.10.1.26 Offset F0h: MCID – Message Signalled Interrupt Capability ID Register
The Message Signalled Interrupt Capability record defines how the device generates
PCI MSI messages. It is an 10B PCI SIG-defined capability record and includes the
MCID, MCP, MCTL, MADR, and MDATA fields of the configuration header.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1302
August 2009
Order Number: 320066-003US