EP80579 Datasheet, PDF (39/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
37.1.1 Terminology and Conventions .................................................................1341
37.1.1.1 Register and Bit References.............................................................1341
37.1.1.2 Byte and Bit Designations ...............................................................1341
37.1.1.3 Numbering....................................................................................1341
37.1.1.4 Memory Alignment Terminology.......................................................1342
37.1.1.5 Alignment and Byte Ordering...........................................................1342
37.1.1.6 Packet Buffer ................................................................................1342
37.1.2 Wake On LAN .......................................................................................1343
37.2 Feature List ...................................................................................................1343
37.3 Functional Block Diagram ................................................................................1344
37.4 Usage Model ..................................................................................................1345
37.4.1 Protocol Translation ...............................................................................1346
37.4.2 Power Management ...............................................................................1346
37.4.3 Software Initialization and Diagnostics .....................................................1346
37.4.3.1 Power Up State .............................................................................1346
37.4.3.2 Memory Initialization ......................................................................1347
37.4.3.3 General Configuration.....................................................................1348
37.4.3.4 Link Setup Mechanisms and Control/Status Bit Summary ....................1348
37.4.3.5 Receive Initialization ......................................................................1348
37.4.3.6 Transmit Initialization.....................................................................1349
37.4.3.7 Initialization of Statistics.................................................................1350
37.4.3.8 GbE Line Rate Configuration Change ................................................1350
37.4.3.9 Network Boot ................................................................................1350
37.4.3.10 Diagnostics ...................................................................................1351
37.5 Functional Description.....................................................................................1351
37.5.1 Ethernet Addressing ..............................................................................1351
37.5.2 Interrupt Control & Tuning .....................................................................1352
37.5.2.1 Interrupt Cause Set/Read Registers..................................................1353
37.5.2.2 Interrupt Mask Set (Read)/Clear Registers ........................................1353
37.5.2.3 Interrupt Throttling Register............................................................1353
37.5.3 Hardware Acceleration Capability ............................................................1353
37.5.3.1 Checksum Off-Loading....................................................................1353
37.5.3.2 TCP Segmentation .........................................................................1354
37.5.4 Buffer and Descriptor Structure...............................................................1354
37.5.5 Packet Reception...................................................................................1354
37.5.5.1 Packet Address Filtering..................................................................1354
37.5.5.2 Receive Data Storage .....................................................................1355
37.5.5.3 Receive Descriptor Format ..............................................................1355
37.5.5.4 Receive Descriptor Fetching ............................................................1358
37.5.5.5 Receive Descriptor Write-Back .........................................................1358
37.5.5.6 Receive Descriptor Queue Structure .................................................1359
37.5.5.7 Receive Interrupts .........................................................................1360
37.5.5.8 Receive Packet Checksum Off loading ...............................................1363
37.5.6 Packet Transmission ..............................................................................1365
37.5.6.1 Transmit Data Storage ...................................................................1365
37.5.6.2 Transmit Descriptor Formats ...........................................................1365
37.5.6.3 Legacy Transmit Descriptor Format ..................................................1366
37.5.6.4 TCP/IP Context Transmit Descriptor Format.......................................1369
37.5.6.5 TCP/IP Data Descriptor Format ........................................................1373
37.5.6.6 Transmit Descriptor Structure..........................................................1375
37.5.6.7 Transmit Descriptor Fetching ...........................................................1377
37.5.6.8 Transmit Descriptor Write-back .......................................................1377
37.5.6.9 Transmit Interrupts........................................................................1378
37.5.6.10 Transmit Checksum Off loading .......................................................1379
37.5.7 TCP Segmentation.................................................................................1380
37.5.7.1 Assumptions .................................................................................1381
37.5.7.2 Transmission Process .....................................................................1381
37.5.7.3 TCP Segmentation Performance .......................................................1382
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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