EP80579 Datasheet, PDF (311/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
12.3
Note:
12.3.1
Throughout this document, all register references are made using the name of the
lower 32-bit register, irrespective of whether the target is a 32-bit or 64-bit register
with lower and upper halves.
Chaining Operation
An EDMA access transfers a block of data from one address to another. The desired
transfer is specified by setting up a linked list of chain descriptors in the local system
memory, and initiated by programming the first chain descriptor start address into the
Next Descriptor Address Registers (NDAR/NDUAR) of the EDMA channel and setting the
Start bit of the Channel Control Register (CCR). Each block of the transfer is defined by
a descriptor in main memory containing the source address, destination address,
transfer length and control values. Setting the Start bit of the Channel Control Register
(CCR) causes the channel to fetch the current chain descriptor information and place it
into its corresponding register set. Once all the register information has been fetched,
the actual data transfer starts.
The Start bit will be ignored unless the Channel Status Register (CSR) is in an
appropriate state. Software must ensure that the status bits for end of chain, stopped,
aborted, and active are all clear prior to attempting to initiate a new transfer with the
start function.
Chain Descriptor Definition
All EDMA transfers are controlled by chain descriptors in the local system memory. A
single block transfer will specify only a single chain descriptor. Chain descriptors can be
linked together to form a linked list, providing a capability for complex EDMA scatter/
gather operations.
Figure 12-3 shows the format of a chain descriptor. Each chain descriptor consists of
eight contiguous DWords (32-bits) in the local system memory, and must be naturally
aligned to an eight Dword boundary. All eight DWords must be defined and are required
for the proper operation of the EDMA engine.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
311