EP80579 Datasheet, PDF (819/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.1.1
Warning:
Note:
23.1.1.1
PCI Header
The default values are defined with an h for hex, a b for binary, or 00 for zero. If there
is not a a letter showing the default value, assume it is a binary number.
Address locations that are not listed are considered reserved register locations. Reads
to reserved registers may return non-zero values and are read only. Writes to reserved
locations may cause system failure and unpredictable results.
Reserved bits are read only.
Offset 00h: ID - Identifiers Register
Table 23-2. Offset 00h: ID – Identifiers Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 00h
Offset End: 03h
Size: 32 bit
Default: Variable
Power Well: Core
Bit Range
31 : 16
15 : 00
Bit Acronym
Bit Description
Sticky
Device ID (DID): The value reported in this field is in the
DID
range between 5028-502Bh. The specific value is
dependent on MAP.SMS, MAP.MV.
VID
Vendor ID (VID): 16-bit field which indicates the
company vendor as Intel.
Bit Reset
Value
Variable
8086h
Bit Access
RO
RO
23.1.1.2 Offset 04h: CMD - Command Register
Table 23-3. Offset 04h: CMD - Command Register (Sheet 1 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 04h
Offset End: 05h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 11
10
09
08
07
06
05
Bit Acronym
Bit Description
Sticky
Reserved
ID
FBE
SEE
WCC
PEE
VGA
Reserved
Interrupt Disable (ID): This disables pin-based INTx#
interrupts. This bit has no effect on MSI operation. When
set, internal INTx# messages will not be generated. When
cleared, internal INTx# messages are generated if there is
an interrupt and MSI is not enabled.
Fast Back-to-Back Enable (FBE): Reserved.
SERR# Enable (SEE): Reserved. The SATA Controller
never generates an SERR#.
Wait Cycle Enable (WCC): Reserved.
Parity Error Response Enable (PEE): When set, the
SATA Controller will corrupt the outbound DATA FIS CRC if
a forwarded data parity error is indicated.
VGA Palette Snooping Enable (VGA): Reserved
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
Bit Access
RO
RW
RO
RO
RO
RW
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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