EP80579 Datasheet, PDF (783/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
20.5.7
SYNC Field/LDRQ# Rules
Since DMA transfers on LPC are requested through an LDRQ# assertion message, and
end through a SYNC field during the DMA transfer, the peripheral must obey the
following rule when initiating back-to-back transfers from a DMA channel.
The peripheral must not assert another message for eight LCLKs after a deassertion is
indicated through the SYNC field. This is needed to allow the 8237, which typically runs
off a much slower internal clock, to see a message deasserted before it is reasserted so
that it can arbitrate to the next agent.
Under default operation, the host only performs 8-bit transfers on 8-bit channels and
16-bit transfers on 16-bit channels. In order to enable 16-bit transfers on 8-bit
channels, the peripheral must communicate to system BIOS that larger transfer sizes
are allowed. If the host has this capability, the BIOS programs the host to attempt
larger transfer sizes. The IICH does not support 32-bit DMA transfer.
The method by which this communication between host and peripheral through system
BIOS is performed is beyond the scope of this specification. Since the host and
peripheral are motherboard devices, no “plug-n-play” registry is required.
The peripheral must not assume that the host is able to perform transfer sizes that are
larger than the size allowed for the DMA channel, and be willing to accept a SIZE field
that is smaller than what it may currently have buffered.
To that end, it is recommended that future devices which may appear on the LPC bus,
which require higher bandwidth than 8-bit or 16-bit DMA allow, do so with a bus
mastering interface and not rely on the 8237.
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August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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