EP80579 Datasheet, PDF (1393/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
RX_DV (receive data valid): This signal is asserted from the PHY to the MAC to
transfer valid frame data to the MAC. It is asserted from the first through the final
bytes of a frame, de-asserted after the final byte. The PHY asserts carrier sense
with this data-valid signal de-asserted to indicate to the MAC reception of broken
packet headers (fragments).
37.5.8.1.2 MII - 10/100 Mbps Operation
During 10/100 Mbps operation (MII mode), the communication between the GbE MAC
and the external PHY occurs via the same interface as in GMII mode, used in a similar
way. In MII mode, transmit and receive data is transferred in nibble-wide (4-bit)
quantities instead of 8-bit quantities, and at either 25Mhz (100 Mbps operation) or 2.5
MHz (10 Mbps operation).
Differences in signaling between GMII and MII modes are as follows:
MTX_CLK (transmit clock): In MII mode, this clock is supplied from the PHY to
the MAC, and is used by the MAC for transmit-data synchronization. This clock
operates at either 25MHz (for 100Base-T) or 2.5MHz (for 10BASE-T).
TX_DATA (transmit data): Transmit data is transferred from the MAC to the PHY
in 4-bit (nibble) quantities at either 25 MHz or 2.5 MHz. in MII mode.
RX_CLK (receive clock): In MII mode, the receive clock provided from the PHY to
the MAC operates at either 25 MHz (for 100BASE-T) or 2.5MHz (for 10BASE-T).
RX_DATA (receive data): Receive data is transferred from the PHY to the MAC in
4-bit (nibble) quantities at either 25 MHz or 2.5 MHz in MII mode.
If a pin is listed in GMII mode, but not MII mode, then it functions identically to GMII
mode.
37.5.8.2
Duplex Operation
The GbE supports half-duplex MII mode and full-duplex GMII/MII mode. Configuration
of the duplex operation of the device must be programmed by software.
37.5.8.2.1 Full Duplex
All aspects of the IEEE 802.3, 802.3u, 802.3z, and 802.3ab specifications are
supported in full duplex operation. During full duplex operation, the GbE may transmit
and receive packets simultaneously across the link interface.
In full-duplex GMII/MII mode, transmission and reception are delineated independently
by the control signals. Transmission starts upon the assertion of TX_EN which indicates
there is valid data on the TX_DATA bus driven from the MAC to the PHY. Reception is
signaled by the PHY by the assertion of the RX_DV signal which indicates valid receive
data on the RX_DATA lines to the MAC.
The GbE can receive carrier-extended packets, although it cannot transmit carrier-
extended packets. Note that errors received the extended portion of the packet
(carrier-extend errors) will not be detected by the GbE.
37.5.8.2.2 Half Duplex
The GbE MAC may operate in half duplex when configured for MII mode, but GMII
mode does not support half duplex operation.
In half duplex operation, the MAC attempts to avoid contention with other traffic on the
link by monitoring the CRS signal provided by the PHY and deferring to passing traffic.
When the CRS signal is de-asserted or after a sufficient inter-packet gap (IPG) has
elapsed after a transmission, frame transmission may begin. The MAC signals the PHY
with TX_EN at the start of transmission.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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