EP80579 Datasheet, PDF (632/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-263.Offset 19Ch: MB_START_ADDR - Memory Test Start Address Register
Description: MB_START_ADDR: Memory Test Start Address
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: 19Ch
Offset End: 19Fh
Size: 32 bit
Default: 00h
Power Well: Core
Bit Range
31 :16
15
14 :03
02 :00
Bit Acronym
Bit Description
ROW
RESERVED
COL
BA
MemBIST Start Row Address 15:0
Reserved
MemBIST Start Column Address
BL8[14:3] <==> DRAM Column Address 15:11,9:3
BL4[14:3] <==> DRAM Column Address 14:11,9:2
MemBIST Start Bank Address 2:0
Sticky
Y
Bit Reset
Value
0000h
0b
Bit Access
RW
RO
Y
0000h
RW
Y
000b
RW
16.5.1.39 Offset 1A0h: MB_END_ADDR - Memory Test End Address Register
This register is only used when MBCSR.atype = 2b’10, and when MBCSR.algo is non-
zero.
Table 16-264.Offset 1A0h: MB_END_ADDR - Memory Test End Address Register
Description: MB_END_ADDR: Memory Test End Address
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: 1A0h
Offset End: 1A3h
Size: 32 bit
Default: 00h
Power Well: Core
Bit Range
31 :16
15
14 :03
02 :0
Bit Acronym
Bit Description
ROW
RESERVED
COL
BA
MemBIST End Row Address 15:0
Reserved
MemBIST End Column Address
BL8[14:3] <==> DRAM Column Address 15:11,9:3
BL4[14:3] <==> DRAM Column Address 14:11,9:2
MemBIST End Bank Address 2:0
Sticky
Y
N
Bit Reset
Value
0000h
0b
Bit Access
RW
RO
Y
0000h
RW
Y
000b
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
632
August 2009
Order Number: 320066-003US