EP80579 Datasheet, PDF (1124/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
30.2.2.8 OCW3[0-1] - Operational Control Word 3 Register
Table 30-13. OCW3[0-1] - Operational Control Word 3 Register
Description:
View: IA F
Base Address: 0000h (IO)
Offset Start: 020h, 0A0h
Offset End: 020h, 0A0h
Size: 8 bit
Default: 001XX10b
Power Well: Core
Bit Range
07
06
05
04 : 03
02
01 : 00
Bit Acronym
Bit Description
Sticky
Reserved
SMM
ESMM
O3S
PMC
RRC
Reserved.
Special Mask Mode:
0 = The Special Mask Mode will not be used by an
interrupt service routine.
1 = The Special Mask Mode can be used by an interrupt
service routine to dynamically alter the system
priority structure while the routine is executing,
through selective enabling/disabling of the other
channel's mask bits. Bit 5, the ESMM bit, must be set
for this bit to have any meaning.
Enable Special Mask Mode:
0 = Disable. The SMM bit becomes a “don't care”.
1 = Enable the SMM bit to set or reset the Special Mask
Mode.
OCW3 Select: When selecting OCW3, bits04:03 = “01”.
Poll Mode Command:
0 = Disable. Poll Command is not issued.
1 = Enable. The next I/O read to the interrupt controller
is treated as an interrupt acknowledge cycle. An
encoded byte is driven onto the data bus,
representing the highest priority level requesting
service.
Register Read Command: These bits provide control for
reading the In-Service Register (ISR) and the Interrupt
Request Register (IRR). When bit 1=0, bit 0 does not
affect the register read selection. When bit 1=1, bit 0
selects the register status returned following an OCW3
read. If bit 0=0, the IRR is read. If bit 0=1, the ISR is
read. Following ICW initialization, the default OCW3 port
address read is “read IRR”. To retain the current selection
(read ISR or read IRR), always write a 0 to bit 1 when
programming this register. The selected register can be
read repeatedly without reprogramming OCW3. To select
a new status register, OCW3 must be reprogrammed prior
to attempting the read.
00 No Action
01 No Action
10 Read IRQ Register
11 Read IS Register
Bit Reset
Value
0h
0h
1
X
X
10b
Bit Access
WO
WO
WO
WO
WO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1124
August 2009
Order Number: 320066-003US