EP80579 Datasheet, PDF (373/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
15.2.1.2
Internal Register Access Mechanism
All SMBus accesses to the internal register space are initiated via a write to the CMD
register. Any register writes received by the IMCH while a command is already in
progress receive a NAK to prevent spurious operation. The master is no longer
expected to poll the CMD register to prevent clobbering a command in progress prior to
issuing further writes. The SMBus access is delayed by stretching the clock until such
time that the data is delivered. Note that per the System Management Bus (SMBus)
Specification, Version 2, this interval can not be longer than 25 ms. To set up an
internal access, the four ADDR bytes are programmed, followed by a command
indicator to execute a read or write. Depending on the type of access, these four bytes
indicate either the Bus number, Device, Function, Extended Register Offset, and
Register Offset; or the Memory-mapped region selected and the address within the
region. The configuration type access utilizes the traditional bus number, device,
function, and register offset; but also uses an extended register offset, which expands
the addressable register space from 256B to 4 KB. The memory-mapped type access
redefines these bytes to be a memory-mapped region selection byte and the memory
address within the region. Table 15-2 and Table 15-3 show this information.
FSB-initiated accesses to registers are serviced through the configuration ring. For
these registers, it is perfectly legal for an SMBus access to be requested while an FSB-
initiated access is already in progress. The IMCH supports “wait your turn” arbitration
to resolve all collisions and overlaps, such that the access that reaches the
configuration ring arbiter first is serviced first while the conflicting access is held off. An
absolute tie at the arbiter is resolved in favor of the FSB. Note that SMBus accesses
must be allowed to proceed even if the internal transaction handling hardware and one
or more of the other external interfaces are hung or otherwise unresponsive.
15.2.1.3 SMBus Register Definitions
15.2.1.3.1
CMD – Command Register
When written, this Command Register indicates the type and size of transfer. All
configuration accesses from the SMBus port are initiated by writing to this register.
While a command is in progress, all future writes or reads are NACK’ed by the IMCH to
avoid overwriting registers while in use. The two command size fields allow for more
flexibility on how the data payload is transferred, both internally and externally. The
begin and end bits support the breaking of the transaction up into smaller transfers, by
defining the start and finish of an overall transfer.
Table 15-4. Command (CMD) Register (Sheet 1 of 2)
Bit
07
06
05
Description
Begin Transaction Indicator
0 = Current transaction is NOT the first of a read or write sequence.
1 = Current transaction is the first of a read or write sequence. On a single transaction sequence
this bit is set along with the End Transaction Indicator.
End Transition Indicator
0 = Current transaction is NOT the last of a read or write sequence.
1 = Current transaction is the last of a read or write sequence. On a single transaction sequence
this bit is set along with the Begin Transaction Indicator.
Address Mode: Indicates whether memory or configuration space is being accessed in this SMBus
sequence.
0 = Memory Mapped Mode
1 = Configuration Register Mode
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
373