EP80579 Datasheet, PDF (950/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 25-16. USBLKMCR - USB Legacy Keyboard/Mouse Control Register (Sheet 2 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:0
Offset Start: C0h
Offset End: C1h
Size: 16 bit
Default: 2000h
Power Well: Core
Bit Range
09
08
07
06
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
TRAPBY60W
SMI Caused by Port 60 Write: Indicates if the event
occurs. Even if the corresponding enable bit is not set in
the Bit 1, then this bit will still be active. It is up to the
SMM code to use the enable bit to determine the exact
cause of the SMI#. Writing a 1 to this bit (in any of the
controllers) will clear the latch. The A20Gate Pass-Through
Logic allows specific port 60h Writes to complete without
setting this bit.
TRAPBY60R
SMI Caused by Port 60 Read: Indicates if the event
occurs. Even if the corresponding enable bit is not set in
the Bit 0, then this bit will still be active. It is up to the
SMM code to use the enable bit to determine the exact
cause of the SMI#. Writing a 1 to this bit (in any of the
controllers) will clear the latch.
SMIATENDPS
SMI at End of Pass-through Enable: This bit enables
SMI at the end of a pass-through. This can occur if an SMI
is generated in the middle of a pass through, and needs to
be serviced later.
0 = Disable
1 = Enable
PSTATE
Pass Through State:
0 = If software needs to reset this bit, it must set bit 5 in
all of the host controllers to 0.
1 = Indicates that the state machine is in the middle of an
A20GATE pass-through sequence.
Note: Software must set bit 5 in all of the host
controllers to 0 to reset this bit.
A20PASSEN
A20Gate Pass-Through Enable:
0 = Disable.
1 = Enable. Allows A20GATE sequence Pass-Through
function. A specific cycle sequence involving writes to
port 60h and 64h does not result in the setting of the
SMI status bits. SMI# will not be generated, even if
the various enable bits are set.
USBSMIEN
SMI on USB IRQ:
0 = Disable. The USB interrupt will not cause an SMI
event.
1 = Enable. The USB interrupt will cause an SMI event.
64WEN
SMI on Port 64 Writes Enable:
0 = Disable. A 1 in bit 11 will not cause an SMI event.
1 = Enable. A 1 in bit 11 will cause an SMI event.
64REN
SMI on Port 64 Reads Enable:
0 = Disable. A 1 in bit 10 will not cause an SMI event.
1 = Enable. A 1 in bit 10 will cause an SMI event.
60WEN
SMI on Port 60 Writes Enable:
0 = Disable. A 1 in bit 9 will not cause an SMI event.
1 = Enable. A 1 in bit 9 will cause an SMI event.
60REN
SMI on Port 60 Reads Enable:
0 = Disable. A 1 in bit 8 will not cause an SMI event.
1 = Enable. A 1 in bit 8 will cause an SMI event.
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
Bit Access
RWC
RWC
RW
RO
RW
RW
RW
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
950
August 2009
Order Number: 320066-003US