EP80579 Datasheet, PDF (1453/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.2.12 PBA – Packet Buffer Allocation Register
This register sets the GbE hardware receive and transmit storage allocation ratio. The
Tx allocation is calculated from the programmed Rx allocation, assuming 64KB of total
Packet Buffer memory.
Note:
Programming this register does not automatically re-load or initialize internal packet-
buffer RAM pointers. The software must reset both transmit and receive operation
(using the global device reset CTRL.RST bit) after changing this register in order for it
to take effect. The PBA register itself will not be reset by assertion of the global reset,
but will only be reset upon initial hardware power-on.
Table 37-36. PBA: Packet Buffer Allocation Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 1000h
Offset End: 1003h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 1000h
Offset End: 1003h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 1000h
Offset End: 1003h
Size: 32 bits
Default: 00100030h
GbE0: Core
Power Well: Gbe1/2:
Core
Bit Range
31 :22
21 : 16
15 :6
5 : 00
Bit Acronym
Bit Description
Sticky
RSVD
TXA
RSVD
RXA
Reserved
Transmit Packet Buffer Allocation in K bytes. PBA.TXA
is read only and calculated based on PBA.RXA.
0010h =>16KB
Reserved
Receive Packet Buffer Allocation in K bytes. PBA.RXA
legal values must be 8K aligned.
Valid values are (decimal) 8, 16, 24, 32, 40, 48, 56.
0030h => 48KBh
Bit Reset
Value
0h
0010h
0h
0030h
Bit Access
RO
RO
RO
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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