EP80579 Datasheet, PDF (696/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
17.1.2
17.1.2.1
Root Complex Topology Capability Structure Registers
The following registers follow the PCI Express capability list structure as defined in the
PCI Express* Specification, to indicate the capabilities of NSI.
Offset 0100h: RCTCL- - Root Complex Topology Capabilities List
Register
Table 17-11. Offset 0100h: RCTCL - Root Complex Topology Capabilities List Register
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 0100h
Offset End: 0103h
Size: 32 bit
Default: 1A010005h
Power Well: Core
Bit Range
31 :20
19 :16
15 :00
Bit Acronym
Bit Description
NEXT
CV
CID
Next Capability: Indicates next item in the list.
Capability Version: Indicates the version of the
capability structure.
Capability ID: Indicates this is a PCI Express link
capability section of an RCRB.
Sticky
Bit Reset
Value
1A0h
1h
Bit Access
RO
RO
0005h
RO
17.1.2.2 Offset 0104h: ES - Element Self Description Register
Table 17-12. Offset 0104h: ESD - Element Self Description Register
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 0104h
Offset End: 0107h
Size: 32 bit
Default: 00000102h
Power Well: Core
Bit Range
31 :24
23 :16
15 :08
07 :04
03 :00
Bit Acronym
Bit Description
Sticky
PN
CID
NLE
Reserved
ET
Port Number: A value of 0 to indicate the egress port for
the IICH.
Component ID: Indicates the component ID assigned to
this element by software. This is written once by platform
BIOS and is locked until a platform reset.
Number of Link Entries: Indicates that one link entry
(corresponding to NSI) is described by this RCRB.
Reserved
Element Type: Indicates that the element type is a root
complex internal link.
Bit Reset
Value
00h
00h
01h
0h
2h
Bit Access
RO
RWO
RO
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
696
August 2009
Order Number: 320066-003US