EP80579 Datasheet, PDF (716/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
18.2.2.3 Offset 03h: TDO - TCO Data Out Register
Table 18-4. Offset 03h: TDO - TCO Data Out Register
Description:
View: PCI
BAR: TCOBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 03h
Offset End: 03h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
TDO
This data register field is used for passing commands
from the SMI handler to the operating system. Writes to
this register sets the TCO_INT_STS bit in the TCO_STS
register. It also causes an interrupt, as selected by the
TCO_IRQ_SEL bits.
Bit Reset
Value
00h
Bit Access
RW
18.2.2.4
Offset 04h: TSTS1 - TCO 1 Status Register
Unless otherwise indicated, these bits are “sticky” and are cleared by writing a one to
the corresponding bit position.
Table 18-5. Offset 04h: TSTS1 - TCO 1 Status Register (Sheet 1 of 3)
Description:
View: PCI
BAR: TCOBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 04h
Offset End: 04h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 13
12
11
10
09
Bit Acronym
Bit Description
Sticky
Reserved Reserved
0 = Software clears this bit by writing a 1 to it.
1 = The IMCH sent a special cycle message NSI
MCHSERR_STS
indicating that it wants to cause an SERR#. The
software must read the IMCH to determine the
reason for the SERR#.
Reserved Reserved.
MCHSMI_STS
0 = Software clears this bit by writing a 1 to it.
1 = IMCH sends a special cycle message indicating that
it wants to cause an SMI. The software must read
the IMCH to determine the reason for the SMI.
MCHSCI_STS
0 = Software clears this bit by writing a 1 to it.
1 = IMCH sends a special cycle message indicating
that it wants to cause an SCI. The software must
read the IMCH to determine the reason for the SCI.
Bit Reset
Value
000h
0h
0h
0h
0h
Bit Access
RO
RWC
RO
RWC
RWC
Intel^® EP80579 Integrated Processor Product Line Datasheet
716
August 2009
Order Number: 320066-003US