EP80579 Datasheet, PDF (1219/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
34.2.2.5
Offset 8h: RID – Revision ID Register
The value of this register comes from the ICH Compatibility Rev ID registers.
Table 34-7. Offset 8h: RID: Revision ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 8h
Offset End: 8h
Size: 8 bit
Default: Variable
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
Revision ID. The 4 most significant bits are always 0. The 4
RID
least significant bits follow the ICH revision ID scheme as
defined in Section 19.2.1.4, “Offset 08h: RID - Revision ID
Register” on page 736.
Bit Reset
Value
Variable
Bit Access
RO
34.2.2.6 Offset 9h: CC – Class Code Register
Table 34-8. Offset 9h: CC: Class Code Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 9h
Offset End: Bh
Size: 24 bit
Default: 060400h
Power Well: Core
Bit Range Bit Acronym
23 : 00
CC
Class Code
Bit Description
Sticky
Bit Reset
Value
060400h
Bit Access
RO
34.2.2.7 Offset Ch: CLS – Cacheline Size Register
Table 34-9. Offset Ch: CLS: Cacheline Size Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: Ch
Offset End: Ch
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range Bit Acronym
07 : 00
CLS
Cacheline Size
Bit Description
Sticky
Bit Reset
Value
0h
Bit Access
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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