EP80579 Datasheet, PDF (1346/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.4.1
37.4.2
37.4.3
37.4.3.1
Protocol Translation
While the GbE’s does not natively support RGMII or RMII a protocol translator is
implemented between the GbE and the pins that converts RGMII to GMII and RMII to
MII for the GbE. Even though the pins may be using an RGMII or RMII protocol the GbE
is still only communicating in its native GMII and/or MII protocols.
The selection of the appropriate translator is controlled by the Auxiliary Device Control
Register. Refer to Section 37.6.2.4, “CTRL_AUX – Auxiliary Device Control/Status
Register”
Note that when the translator selection register has enabled RGMII, the GbE must be
configured to GMII/MII operation. Likewise, when the settings have enabled RMII, the
GbE must be configured to MII operation.
Power Management
As shown in Figure 37-2, “GbE Ethernet Complex” on page 1345, GbE0 is located in a
separate auxiliary power well. This gives the user the ability to bring the rest of the chip
into an ultra-low power mode (power removed) while GbE0 continues to operate in
D3cold to support Wake On LAN. If a separate auxiliary power source is used for GbE0,
then platform must also supply an Aux_Pwr_Good signal which is asserted to indicate
that the auxiliary power supply is stable and that the reference clock for the GbE is
stable. Additionally, the EEDI pin should be pulled-up to provide the internal
aux_pwr_present signal indicating that an auxiliary supply is being used. If an auxiliary
power supply is not being used and the power supplied to the auxiliary well is the same
as that for the core logic, then EEDI must be tied low. In this situation the same signal
as provided to Sys_Pwr_OK is also routed to Aux_Pwr_Good.
Note that if an auxiliary supply is used for GbE0 then the corresponding PHY and also
the serial EEPROM, if present, must be powered.
Refer to the Section 6.3.2, “Power Management Support”and Section 37.5.10, “Wake
on LAN” for more details.
Software Initialization and Diagnostics
This section discusses general software notes for the GbE, especially initialization steps.
This includes general hardware power-up state, basic device configuration, initialization
of transmit and receive operation, link configuration, software reset capability,
statistics, and diagnostic hints.
Power Up State
When the MAC powers up it will read the optional EEPROM. The EEPROM contains
sufficient information to bring the link up and configure the MAC for manageability and/
or APM wakeup. However, software initialization is required for normal operation and if
the EEPROM is not present.
The power-up sequence, as well as transitions between power states, is described in
Section 37.7.3, “Power States” on page 1550. The detailed timing is given in Section
37.7.4, “Timing of Power-State Transitions” on page 1551. Section 37.6, “GbE
Controller Register Summary” on page 1425 gives detailed registers descriptions with
details on power on defaults.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1346
August 2009
Order Number: 320066-003US