EP80579 Datasheet, PDF (1348/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.4.3.3
37.4.3.4
37.4.3.5
General Configuration
Several values in the CTRL – Device Control Register, CTRL_EXT – Extended Device
Control Register and CTRL_AUX – Auxiliary Device Control/Status Register need to be
set upon power up or after a device reset for normal operation.
• Convergence Layer Mode of the MAC is programmed by the CTRL_EXT.LINK_MODE
setting. This value may also be read by software from the STATUS – Device Status
Register at STATUS.TBIMODE.
• Duplex mode is determined via Auto-Negotiation between the external PHY and it’s
link partner. Software either continuously polls the PHY registers via MDIO until a
link is detected or the host CPU is interrupted when the link is established via the
PHY’s MDINT capability. Software then programs CTRL.FD per the interface
negotiation. Status information can be found at STATUS.FD.
• Speed is determined via Auto-Negotiation between the external PHY and it’s link
partner. Software either continuously polls the PHY registers via MDIO until a link is
detected or the host CPU is interrupted when the link is established. Software then
programs CTRL.SPEED per the interface negotiation. Status information can be
found at STATUS.SPEED.
• Desired endianness configuration must be set in CTRL_AUX.
Link Setup Mechanisms and Control/Status Bit Summary
• MAC duplex and speed settings forced by software based on resolution of PHY
— CTRL.FD and CTRL.SPEED is set by software based on reading PHY status
register after PHY has successfully auto-negotiated a link with the link partner.
— CTRL.RFCE and CTRL.TFCE must be set by software after reading flow control
resolution from PHY registers
Receive Initialization
Software must program the Receive Address Low Register (RAL) and Receive Address
High Register (RAH) registers to represent the receive address(es) per the station
address. The station address (a.k.a the MAC address) is RAL/RAH(0), fifteen additional
receive addresses can be programmed in addition to this.
Software must also set up the 128 Multicast Table Array Registers (MTA[127:0]). This
probably means zeroing all entries initially and adding in entries to the Multicast Table
Array as requested.
Figure 37-3 diagrams the multicast lookup algorithm. The destination address shown
represents the internally stored ordering of the received Destination Address. Note that
bit 0 indicated in this diagram is the first on the wire. Refer to “Ethernet Addressing” on
page 1351 for more details. Note that the bank bits is the RCTL.MO setting.
Program the Interrupt Mask Set/Read Register (IMS) to pass any interrupt the driver
cares about to the Interrupt Controller for routing further to the EP80579’s IA-32 core.
Suggested bits include IMS.RXT0, IMS.RXO, and IMS.RXDMT0.
Program Receive Control Register (RCTL) with appropriate values. If initializing, it is
necessary to leave the receive logic disabled, RCTL.EN = 0, until after the receive
descriptor ring has been initialized. If VLANs are not used, software should clear
RCTL.VFE. Then there is no need to initialize the 128 VLAN Filter Table Array Registers
(VFTA[127:0]). Initialize the remainder of RCTL as desired, refer to “Section 37.6.4.1,
“RCTL – Receive Control Register”” or details.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1348
August 2009
Order Number: 320066-003US