EP80579 Datasheet, PDF (302/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
11.4.4
Note:
11.4.5
Refresh
The EP80579 supports generation of the refresh commands (REF) that are necessary
for the DRAM devices to retain its data. When the refresh cycle is launched by memory
controller an address counter, internal to the DRAM device, supplies the bank address
during the refresh cycle. No control of the address bus is required for a refresh cycle.
When the refresh cycle has completed, all banks of the DDR2 device will be in the
precharged (idle) state. A delay between the Refresh command and the next activate
command or subsequent Refresh command must be greater than or equal to the
Refresh cycle time (tRFC). There are 3 mechanisms through which the EP80579
memory controller will generate the refresh commands:
1. Programmable counter: The refresh engine can be programmed to generate
refresh commands at programmable time intervals. The choice of intervals are
meant to cover DDR2 device tREFI specifications. Please refer to Section 16.5.1.3,
“Offset 40h: DCALCSR – DDR Calibration Control and Status Register” details on
programming the refresh engine.
2. Programmable OPCODE generation: A single refresh command can be
generated under software control using the available opcodes in Section 16.5.1.3,
“Offset 40h: DCALCSR – DDR Calibration Control and Status Register”.
3. Self-Refresh exit state machine: The self-refresh exit engine will issue one
refresh command to each rank after it brings them out of self refresh.
The EP80579 does not support posted refresh cycles.
Self-Refresh
The EP80579 supports the generation of self-refresh commands that can be used to
retain data in the DRAM devices without any support from the memory controller. The
DRAM device has built-in counters timers to accommodate the self-refresh operation.
There are 2 mechanisms to enter and exit the self-refresh mode:
1. Self-Refresh Entry
a. S3: The memory controller will issue a self-refresh entry command at the end
of the S3 sequence.
b. Programmable OPCODE generation: A self-refresh entry command can be
generated under software control using the available opcodes Section 16.5.1.3,
“Offset 40h: DCALCSR – DDR Calibration Control and Status Register”.
2. Self-Refresh Exit
a. Power up after S3 event: The memory controller implements a self-refresh
exit engine which under software control can bring the DRAM devices out of self-
refresh. Refer to Table 16-226, “Rules about issuing Self-Refresh and Refresh
commands using DCALCSR.OPCODE” on page 604 for details on the rules that
software should follow when using this mechanism.
b. Writing to DRC.CKE[1:0] register bits: By writing to the DRC.CKE[1:0]
registers, software can assert the CKE pins to the DRAM devices bringing them
out of self-refresh.Please refer to Section 16.5.1.59, “Offset 1F4h:
MB_ERR_DATA32 - Memory Test Error Data 3” for more details.
The de-emphasis feature on the command/clock pins should be disabled before
entering self-refresh. Please see the DEMCA bit in Section 16.5.1.63, “Offset 264h:
DDRIOMC1 - DDR IO Mode Control Register 1” for more details.
Intel^® EP80579 Integrated Processor Product Line Datasheet
302
August 2009
Order Number: 320066-003US