EP80579 Datasheet, PDF (12/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
16.1.1.34 Offset CCh: TOM - Top Of Memory Register ........................................ 417
16.1.1.35 Offset CEh: HECBASE - PCI Express Port A (PEA) Enhanced Configuration
Base Address Register ..................................................................... 418
16.1.1.36 Offset D8h: CACHECTL0 - Write Cache Control 0 Register ..................... 418
16.1.1.37 Offset DEh: SKPD - Scratchpad Data Register ..................................... 419
16.1.1.38 Offset F6h: IMCH_TST2 - IMCH Test Byte 2 Register ............................ 419
16.1.1.39 Offset 60h: DRB[0-3] – DRAM Row [3:0] Boundary Register ................. 420
16.1.1.40 Offset 70h: DRA[0-1] – DRAM Row [0:1] Attribute Register .................. 421
16.1.1.41 Offset 78h: DRT0 - DRAM Timing Register 0 ....................................... 424
16.1.1.42 Offset 64h: DRT1 – DRAM Timing Register 1 ....................................... 431
16.1.1.43 Offset 7Ch: DRC – DRAM Controller Mode Register .............................. 435
16.1.1.44 Offset 84h: ECCDIAG – ECC Detection/Correction
Diagnostic Register.......................................................................... 437
16.1.1.45 Offset 88h: SDRC – DDR SDRAM Secondary Control Register ................ 439
16.1.1.46 Offset 8Ch: CKDIS – CK/CK# Clock Disable Register ............................ 441
16.1.1.47 Offset 8Dh: CKEDIS - CKE Clock Disable Register ................................ 442
16.1.1.48 Offset 90h: SPARECTL - SPARE Control Register .................................. 443
16.1.1.49 Offset B0h: DDR2ODTC - DDR2 ODT Control Register .......................... 443
16.2 DRAM Controller Error Reporting Registers: Bus 0, Device 0, Function 1 ................. 445
16.2.1 Register Details ...................................................................................... 447
16.2.1.1 Offset 00h: VID - Vendor Identification Register .................................. 447
16.2.1.2 Offset 02h: DID - Device Identification Register .................................. 447
16.2.1.3 Offset 04h: PCICMD - PCI Command Register ..................................... 448
16.2.1.4 Offset 06h: PCISTS - PCI Status Register ........................................... 448
16.2.1.5 Offset 08h: RID - Revision Identification Register ................................ 449
16.2.1.6 Offset 0Ah: SUBC - Sub-Class Code Register....................................... 449
16.2.1.7 Offset 0Bh: BCC - Base Class Code Register........................................ 449
16.2.1.8 Offset 0Dh: MLT - Master Latency Timer Register ................................ 450
16.2.1.9 Offset 0Eh: HDR - Header Type Register............................................. 450
16.2.1.10 Offset 2Ch: SVID - Subsystem Vendor Identification Register ................ 450
16.2.1.11 Offset 2Eh: SID - Subsystem Identification Register............................. 451
16.2.1.12 Offset 40h: GLOBAL_FERR - Global First Error Register......................... 451
16.2.1.13 Offset 44h: GLOBAL_NERR - Global Next Error Register........................ 453
16.2.1.14 Offset 48h: NSI_FERR - NSI First Error Register .................................. 454
16.2.1.15 Offset 4Ch: NSI_NERR - NSI Next Error Register ................................. 457
16.2.1.16 Offset 50h: NSI_SCICMD - NSI SCI Command Register ........................ 459
16.2.1.17 Offset 54h: NSI_SMICMD - NSI SMI Command Register ....................... 461
16.2.1.18 Offset 58h: NSI_SERRCMD - NSI SERR Command Register ................... 464
16.2.1.19 Offset 5Ch: NSI_MCERRCMD - NSI MCERR Command Register .............. 466
16.2.1.20 Offset 60h: FSB_FERR - FSB First Error Register.................................. 468
16.2.1.21 Offset 62h: FSB_NERR - FSB Next Error Register ................................. 469
16.2.1.22 Offset 64h: FSB_EMASK - FSB Error Mask Register .............................. 470
16.2.1.23 Offset 68h: FSB_SCICMD - FSB SCI Command Register ....................... 471
16.2.1.24 Offset 6Ah: FSB_SMICMD - FSB SMI Command Register....................... 472
16.2.1.25 Offset 6Ch: FSB_SERRCMD - FSB SERR Command Register .................. 473
16.2.1.26 Offset 6Eh: FSB_MCERRCMD - FSB MCERR Command Register .............. 474
16.2.1.27 Offset 70h: BUF_FERR - Memory Buffer First Error Register .................. 475
16.2.1.28 Offset 72h: BUF_NERR - Memory Buffer Next Error Register.................. 475
16.2.1.29 Offset 74h: BUF_EMASK - Memory Buffer Error Mask Register ............... 476
16.2.1.30 Offset 78h: BUF_SCICMD - Memory Buffer SCI Command Register ........ 477
16.2.1.31 Offset 7Ah: BUF_SMICMD - Memory Buffer SMI Command Register ....... 478
16.2.1.32 Offset 7Ch: BUF_SERRCMD - Memory Buffer SERR
Command Register .......................................................................... 479
16.2.1.33 Offset 7Eh: BUF_MCERRCMD - Memory Buffer MCERR
Command Register .......................................................................... 480
16.2.1.34 Offset E4h: NSIERRINJCTL - NSI Error Injection Control Register ........... 481
16.2.1.35 Offset E8h: BERRINJCTL - Buffer Error Injection Control Register........... 481
16.2.1.36 Offset 80h: DRAM_FERR - DRAM First Error Register ............................ 482
16.2.1.37 Offset 82h: DRAM_NERR - DRAM Next Error Register ........................... 484
16.2.1.38 Offset 84h: DRAM_EMASK - DRAM Error Mask Register ........................ 485
Intel^® EP80579 Integrated Processor Product Line Datasheet
12
August 2009
Order Number: 320066-003US