EP80579 Datasheet, PDF (1326/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 35-161.Offset 2Eh: SID: Subsystem ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:8:0
Offset Start: 2Eh
Offset End: 2Fh
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
15 : 00
SID
Subsystem ID: This field must be programmed during
BIOS initialization.
Sticky
Bit Reset
Value
Bit Access
0h
RWO
35.12.1.12 Offset 34h: CP – Capabilities Pointer Register
Table 35-162.Offset 34h: CP: Capabilities Pointer Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:8:0
Offset Start: 34h
Offset End: 34h
Size: 8 bit
Default: DCh
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 00
Pointer to First Capability Structure: Value is DCh
CP
which is the config space offset of the first capability
structure.
Sticky
Bit Reset
Value
Bit Access
DCh
RO
35.12.1.13 Offset 3Ch: IRQL – Interrupt Line Register
Table 35-163.Offset 3Ch: IRQL: Interrupt Line Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:8:0
Offset Start: 3Ch
Offset End: 3Ch
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
IRQL
Interrupt Line: BIOS writes the interrupt routing
information to this register to indicate which input of the
interrupt controller this device is connected to.
Bit Reset
Value
0h
Bit Access
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1326
August 2009
Order Number: 320066-003US