EP80579 Datasheet, PDF (1039/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
26.13.2.2 Offset A4h: USBPID - USB PIDs Register
This Dword register is used to communicate PID information between the USB debug
driver and the USB debug port. The debug port uses some of these fields to generate
USB packets, and uses other fields to return PID information to the USB debug driver.
Table 26-56. Offset A4h: USBPID - USB PIDs Register
Description:
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: A4h
Offset End: A4h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
31 :24
23 :16
15 :08
07 :00
Reserved Reserved.
The hardware updates this field with the received PID for
transactions in either direction. When the controller is
writing data, this field is updated with the handshake PID
RECEIVED_PID_ that is received from the device. When the host controller
STS
is reading data, this field is updated with the data packet
PID (if the device sent data), or the handshake PID (if the
device NAKs the request). This field is valid when the
hardware clears the GO_DONE#_CNT bit.
The hardware sends this PID to begin the data packet
SEND_PID_CNT
when sending data to USB (i.e., WRITE_READ#_CNT is
asserted). Software will typically set this field to either
DATA0 or DATA1 PID values.
TOKEN_PID_CN
T
The hardware sends this PID as the Token PID for each
USB transaction. Software will typically set this field to
either IN, OUT or SETUP PID values.
Bit Reset
Value
0h
0h
0h
0h
Bit Access
RO
RW
RW
26.13.2.3 Offset A8h: DATABUF - Data Buffer Bytes 7:0
Note:
This register can be accessed as eight separate 8-bit registers or two separate 32-bit
registers.
Table 26-57. Offset A8h: DATABUF - Data Buffer Bytes 7:0
Description:
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: A8h
Offset End: AFh
Size: 64 bit
Default: 0000000000000000h
Power Well: Core
Bit Range
63 :00
Bit Acronym
Bit Description
Sticky
DATABUFFER
These are the 8 bytes of the data buffer. Bits 7:0
correspond to least significant byte (byte 0). Bits 63:56
correspond to the most significant byte (byte 7).
The bytes in the Data Buffer must be written with data
before software initiates a write request. For a read
request, the Data Buffer contains valid data when
DONE_STS is set by the hardware, ERROR_GOOD#_STS
is cleared by the hardware, and the DATA_LENGTH_CNT
field indicates the number of bytes that are valid.
Bit Reset
Value
0h
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1039