EP80579 Datasheet, PDF (541/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.21 Offset 28h: PMBASU - Prefetchable Memory Base
Upper Address Register
These register expands the prefetchable memory base address by four bits. All other
bits are reserved.
Table 16-160.Offset 28h: PMBASU - Prefetchable Memory Base Upper Address Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 28h
Offset End: 28h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 28h
Offset End: 28h
Size: 8 bit
Default: 0Fh
Power Well: Core
Bit Range
07 : 04
03 : 00
Bit Acronym
Bit Description
Sticky
Reserved
BUA
Reserved
Base Upper Address bits: These four bits expands the
prefetchable address base to 36 bits. Corresponds to
A[35:32] of the lower limit of the address range passed by
bridge device across the PCI Express* interface.
Bit Reset
Value
0h
Fh
Bit Access
RW
16.4.1.22 Offset 2Ch: PMLMTU - Prefetchable Memory Limit Upper
Address Register
These register expands the prefetchable memory limit address by four bits. All other
bits are reserved.
Table 16-161.Offset 2Ch: PMLMTU - Prefetchable Memory Limit Upper Address Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 2Ch
Offset End: 2Ch
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 2Ch
Offset End: 2Ch
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 04
03 : 00
Bit Acronym
Bit Description
Sticky
Reserved
LUA
Reserved
Limit Upper Address bits: These four bits expands the
prefetchable address limit to 36 bits. Corresponds to
A[35:32] of the upper limit of the address range passed by
bridge device across the PCI Express* interface.
Bit Reset
Value
0h
0h
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
541