EP80579 Datasheet, PDF (52/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
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Bus 0 Device Map ............................................................................................. 348
NSI Type 0 Configuration Address Translation ...................................................... 350
NSI Type 1 Configuration Address Translation ...................................................... 351
Mechanism #1 Type 1 Configuration Address to PCI Address Mapping...................... 351
IMCH Configuration Flow Chart ........................................................................... 352
PCI Express Configuration Transaction Header ...................................................... 356
Enhanced Configuration Memory Address Map ...................................................... 357
Global FERR/NERR Register Representation .......................................................... 362
FERR/NERR Service Routine ............................................................................... 364
PCI Express Error Handling ................................................................................ 368
Dword Configuration Read Protocol ..................................................................... 377
Dword Configuration Write Protocol ..................................................................... 377
Dword Memory Read Protocol............................................................................. 377
Dword Memory Write Protocol ............................................................................ 377
Dword Configuration Read Protocol ..................................................................... 378
Dword Configuration Write Protocol ..................................................................... 378
Dword Memory Read Protocol............................................................................. 379
Dword Configuration Write Protocol ..................................................................... 379
LPC Interface Diagram ...................................................................................... 758
LPC Bridge SERR# ........................................................................................... 762
IICH DMA Controller.......................................................................................... 763
DMA Request Assertion through LDRQ#............................................................... 780
Basic SPI Protocol ............................................................................................. 787
Legacy Mode Host Controller Power State Hierarchy .............................................. 880
Hardware Flow for Port Enable/Device Present Bits................................................ 883
Port System Memory Structure ........................................................................... 884
Power State Hierarchy ....................................................................................... 890
Example Queue Conditions................................................................................. 967
USB Data Encoding ........................................................................................... 970
USB Port Connections...................................................................................... 1033
C0→C2→C0 Entry/Exit Timings......................................................................... 1081
Coprocessor Error Timing Diagram .................................................................... 1103
Example UART Data Frame .............................................................................. 1173
WDT Block Diagram ........................................................................................ 1193
Start Frame Timing with Source Sampled a Low Pulse on IRQ1 ............................. 1203
Stop Frame Timing with Host Using Quiet Mode Sampling Period........................... 1203
PCI Configuration Command Register Layout ...................................................... 1234
PCI Configuration Status Register Layout ........................................................... 1234
PCI Power Management Register Block .............................................................. 1236
GbE Controller Block Diagram........................................................................... 1344
GbE Ethernet Complex .................................................................................... 1345
Multicast Table Array Algorithm ........................................................................ 1349
Example Address Byte Ordering........................................................................ 1352
DA Byte Ordering ........................................................................................... 1352
Receive Descriptor (RDESC) Layout................................................................... 1355
Receive Status (RDESC.Status) Layout .............................................................. 1356
Receive Errors (RDESC.ERRORS) Layout ............................................................ 1357
Special Descriptor Field Layout ......................................................................... 1358
Receive Descriptor Ring Structure ..................................................................... 1359
Packet Delay Timer operation illustrated with a state diagram............................... 1361
Case A: Using only an Absolute Timer ............................................................... 1361
Case B: Using an Absolute Timer in conjunction with the Packet Timer................... 1362
Case C: Packet Timer Expires Even Though A Packet Was Being Transferred
to the Host Memory. ....................................................................................... 1362
IPv6 Extension Header Structure ...................................................................... 1364
Intel^® EP80579 Integrated Processor Product Line Datasheet
52
August 2009
Order Number: 320066-003US