EP80579 Datasheet, PDF (938/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 24-58. Data Values for Slave Read Registers (Sheet 2 of 2)
Register
4
5
6
7
8
9
A
B
C – FFh
Bits
00
01
02
03
06:04
07
00
01
02
07:01
07:00
07:00
07:00
07:00
07:00
07:00
07:00
Description
1 = The Intruder Detect (INTRD_DET) bit is set. This indicates that the system cover has
been opened.
1 = BTI Temperature Event occurred. This bit is set if the CMI’s PROCHOT# input signal is
active. Need to take after polarity control.
DOA processor Status. This bit is 1 to indicate that the processor is dead.
1 = SECOND_TO_STS bit set. This bit is set after the second timeout (SECOND_TO_STS bit)
of the Watchdog Timer occurs.
Reserved. Will always be 0, but software should ignore.
Reflects the value of the GPI[11]/SMBALERT# pin (and is dependent upon the value of the
GPI_INV[11] bit. If the GPI_INV[11] bit is 1, then the value in this bit equals the level of the
GPI[11]/SMBALERT# pin (high = 1, low = 0).
If the GPI_INV[11] bit is 0, then the value of this bit equals the inverse of the level of the
GPI[11]/SMBALERT# pin (high = 0, low = 1).
FWH bad bit. This bit is 1 to indicate that the FWH read returned FFh, which indicates that it
is probably blank.
Battery Low Status. ‘1’ if the BATLOW# pin is a ‘0’.
CPU Power Failure Status: ‘1’ if the CPUPWR_FLR bit in the GEN_PMCON_2 register is set.
Reserved
Contents of the Message 1 register. See Section 18.2.2.8 for details.
Contents of the Message 2 register. See Section 18.2.2.8 for details.
Contents of the WDSTATUS register. See Section 18.2.2.9 for details.
Contents of the SATA SGPIO Control Register (bits 07:00). See Section 48.3.3.1 for details.
Contents of the SATA SGPIO Control Register (bits 15:08). See Section 48.3.3.1 for details.
Contents of the SATA SGPIO Control Register (bits 23:16). See Section 48.3.3.1 for details.
Reserved
Warning:
The external microcontroller is responsible to make sure that it does not read the
contents of the various message registers until they have been written by the system
processor. The CMI overwrites the old value with any new value received. A race
condition is possible where the new value is being written to the register just at the
time it is being read. The CMI does not attempt to cover this race condition (i.e.,
unpredictable results in this case).
Behavioral Notes:
The SMBus protocol always has either start bit-address-write bit or repeated start bit-
address-read bit. The CMI is implemented such that the read/write bit in the repeated
start phase is ignored with an assumption that the protocol always followed. In other
words, if start-address-read occurs (which is illegal for SMBus byte read protocol), the
CMI still grabs the cycle. In another case, if a repeated start-address-write sequence
occurs, then the cycle continues as a slave read.
24.9.3
Format of the Host Notify Command
The CMI tracks and responds to the standard Host Notify command as specified in the
SMBus Specification. The host address for this command is fixed to 0001000b. If the
CMI already has data for a previously-received host notify command which has not
been serviced yet by the host software (as indicated by the HOST_NOTIFY_STS bit),
then it will NACK following the host address byte of the protocol. This allows the host to
communicate non-acceptance to the master and retain the host notify address and
data values for the previous cycle until host software completely services the interrupt.
Intel^® EP80579 Integrated Processor Product Line Datasheet
938
August 2009
Order Number: 320066-003US