EP80579 Datasheet, PDF (95/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 1-2.
Related Websites
Specification or Technology
Website
AC’97 Rev 2.2 Specification
ACPI and related specifications
AT Attachment-6 with Packet Interface (ATA/ATAPI-6)
BIOS Boot Specifications
Communication and Network Riser Rev 1.2
Specification
Front Panel I/O Connectivity Design Guide
PCI and PCI Express* related specifications
PIRQ Routing Table Information
Power Management Specifications
http://developer.intel.com/ial/scalableplatforms/
audio/index.htm #97spec/
http://www.acpi.info/spec.htm
http://T13.org (T13 1410D)
http://www.phoenix.com/en/customer+services/
white+papers-specs/
http://developer.intel.com/technology/cnr/
download.htm
http://www.formfactors.org/DeveloperResources.asp
http://www.pcisig.com/specifications
http://www.microsoft.com/whdc/archive/pciirq.mspx
http://www.microsoft.com/whdc/resources/respec/
specs/pmref/default.mspx
1.4
Acronyms
This section describes acronyms that are used throughout this document.
Table 1-3. Acronym Table
Term
ACPI
AHCI
AIO
AIOC
AMC
ARP
ASF
ASU
BAR
BER
BGA
CM
CMC
CMI
CNR
CRC
CSMA/CD
DDP
DDR
Description
Advanced Configuration and Power Interface Specification, an industry specification of the
common interfaces enabling robust operating system (OS)-directed motherboard device
configuration and power management of both devices and entire systems.
Advanced Host Controller Interface, an industry specification of the interface between
memory and SATA devices.
IMCH A-unit I/O Mux Leg
Acceleration and I/O Complex
Audio/Modem Codec
Address resolution protocol
Alert Specification Format. This is the next generation of “Alert on LAN*” implementation.
Acceleration Services Unit
PCI Base Address Register used to define the base and limit of an I/O or memory region
assigned to a PCI device.
Bit Error Rate
Ball Grid Array
Coherent Memory
Common Mode Choke
Core (IA-32 core) interface, Memory controller hub, I/O controller hub
Communications and Networking Riser
See Cyclic Redundancy Check in Table 1-4.
Carrier Sense Multiple Access/Carrier Detect
Direct Data Placement Protocol
DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) is a
system memory technology.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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