EP80579 Datasheet, PDF (1199/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
33.6.2.9 Offset 0Dh: RR1 - Reload Register 1
Table 33-34. Offset 0Dh: RR1 - Reload Register 1
Description:
View: IA F
Base Address: Base (IO)
Offset Start: 0Dh
Offset End: 0Dh
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
TOUT
RELOAD
Reserved
WDT_TIMEOUT: This bit is located in the RTC Well and
it’s value is not lost if the host resets the system. It is set
to ‘1’ if the host fails to reset the WDT before the 35-bit
Down-Counter reaches zero for the second time in a row.
This bit is cleared by performing the Register Unlocking
Sequence followed by a ‘1’ to this bit.
0 = Normal (Default)
1 = System has become unstable.
Note: In free running mode this bit is set every time the
down counter reaches zero.
WDT_RELOAD: To prevent a timeout the host must
perform the Register Unlocking Sequence followed by a ‘1’
to this bit.
Refer to Section 33.6.3.2 for details on how to change the
value of this register.
Bit Reset
Value
00h
0h
0h
Bit Access
RW
RW
33.6.2.10 Offset 10h: WDTCR - WDT Configuration Register
Table 33-35. Offset 10h: WDTCR - WDT Configuration Register (Sheet 1 of 2)
Description:
View: IA F
Base Address: Base (IO)
Offset Start: 10h
Offset End: 10h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 06
05
Bit Acronym
Bit Description
Sticky
Reserved Reserved
WDT Timeout Output Enable: This bit indicates whether
or not the WDT toggles the external WDT_TOUT# pin if
WDT_TOUT_EN ^{the WDT times out.}
0 = Enabled (Default)
1 = Disabled
Bit Reset
Value
00h
0h
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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