EP80579 Datasheet, PDF (723/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
18.2.2.11 Offset 12h: TTMR - TCO Timer Initial Value Register
Table 18-12. Offset 12h: TTMR - TCO Timer Initial Value Register
Description:
View: PCI
BAR: TCOBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 12h
Offset End: 13h
Size: 16 bit
Default: 0004h
Power Well: Core
Bit Range
15 : 10
09 : 00
Bit Acronym
Bit Description
Sticky
Reserved
TTMR
Reserved
Value that is loaded into the timer each time the
TCO_RLD register is written. Values of 0000h or 0001h
are ignored and must not be attempted. The timer is
clocked at approximately 0.6 s, and thus allows
timeouts ranging from 1.2 s to 613.8 s.
Note: The timer has an error of +/- 1 tick (0.6 s). The
TCO Timer only counts down in the S0 state.
Bit Reset
Value
00h
004h
Bit Access
RO
RW
18.3
18.3.1
18.3.2
18.3.3
18.4
18.4.1
TCO Signal Usage
INTRUDER# Signal
This signal can be used to detect the chassis being opened. The activation of this signal
can be used to cause an SMI#, and is reported via the event mechanism. If SMI# is
desired, the signals level can be read, so this can be used as a type of general purpose
input.
Pin Straps
Some of the TCO functions are decided at power up (rising edge of PWROK). See the
pinlist for specific assignments of pin straps.
SMLINK Signals
The CMI supports TCO compatible mode connectivity. TheIICHsupports External LAN
controllers. An external LAN Controller can be used to receive or retrieve TCO message
or information on Host SMBus if needed. In Legacy TCO mode messages are driven via
SMLink.
For the CMI, messages on this link use SMBus protocol at the rates described in
Chapter 24.0, “SMBus Controller Functional Description: Bus 0, Device 31, Function 3,”
for TCO compatible mode.
TCO Theory of Operation
Overview
The system management functions are designed to allow the system to diagnose failing
subsystems. The intent of this logic is that the system management functionality be
provided without the aid of an external micro controller.
The CMI’s System Management logic allows for diagnostic and recovery software to be
distributed between an SMI handler and operating system-based code.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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