EP80579 Datasheet, PDF (1603/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
39.6.1.17 Offset 000000B8h: RxMessageAMR_Data[0-15] - Receive Message
AMR Data
Note:
These registers are implemented in the SRAM which does not have the capability to
mask writes to reserved bits. Therefore, reserved bits in this CSR will be RW. Software
should treat these bits as reserved and not change the reset value of these bits.
Note:
These registers are implemented in SRAM which is not initialized at power-up or upon
reset. So before enabling the CAN, software needs to update these CSR’s with the reset
values.
Table 39-22. Offset 000000B8h: RxMessageAMR_Data[0-15] - Receive Message AMR Data
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:4:0
000000B8h
Offset Start: at 20h
Offset End: 000000BBh
at 20h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:5:0
000000B8h
Offset Start: at 20h
Offset End: 000000BBh
at 20h
Size: 32 bit
Default: XXXXXXXXh
Power Well: Core
Bit Range
31 :16
15 :00
Bit Acronym
Bit Description
RSVD
Reserved
Data_63_48 Data (bits [63:48])
Sticky
Bit Reset
Value
Xh
Xh
Bit Access
RW
RW
39.6.1.18 Offset 000000BCh: RxMessageACR_Data[0-15] - Receive Message
ACR Data
Note:
These registers are implemented in the SRAM which does not have the capability to
mask writes to reserved bits. Therefore, reserved bits in this CSR will be RW. Software
should treat these bits as reserved and not change the reset value of these bits.
Note:
These registers are implemented in SRAM which is not initialized at power-up or upon
reset. So before enabling the CAN, software needs to update these CSR’s with the reset
values.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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