EP80579 Datasheet, PDF (518/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.3.1.23 Offset B0h: MSICR - MSI Control Register
The EDMA controller generates an upstream interrupt message using Message Signaled
Interrupts (MSI) to the processor, bypassing the IOxAPIC. The MSI is generated by a
memory write to address 0FEEx_xxxxh. The MSI Control Register (MSICR), MSI
Address Register (MSIAR) and MSI Data Register (MSIDR) support this mechanism.
The default values of these registers are compatible with the default value of IOxAPIC.
System software can reprogram these values, if required.
The MSI Control Register (MSICR) contains all the information related to the capability
of EDMA MSI interrupts.
Table 16-135.Offset B0h: MSICR - MSI Control Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:1:0
Offset Start: B0h
Offset End: B3h
Size: 32 bit
Default: 00020005h
Power Well: Core
Bit Range
31 : 24
23
22 : 20
19 : 17
16
15 : 08
07 : 00
Bit Acronym
Bit Description
Sticky
Reserved
ADDCPBL
MME
MMC
MSIE
NXT_PTR
CAP_ID
Reserved.
Indicates 64-bit Address Capable: Hardwired to 0 to
indicate that the EDMA Controller is capable of 32-bit MSI
addressing only.
Multiple Message Enable: The software writes to this
field to indicate the number of allocated messages, which
is aligned to a power of two. The value programmed into
this field must be less than or equal to the number
requested in the Multiple Messages Capable field.
When MSI is enabled, the software allocates at least one
message to the device. If two MSI messages are enabled,
Message 0 is used for normal interrupts, and Message 1 is
used for abort/error interrupts. If only one MSI message is
enabled, Message 0 is used for both normal and error
interrupts.
Multiple Message Capable: Hardwired to a value of 001b
to indicate that the EDMA requests a capability for two
messages.
MSI Enable: Interrupts are generated for the conditions
as described in the descriptor control register for each
channel. If none of these conditions are selected, software
must poll for status since no interrupts of either type are
generated.
0 = Legacy interrupts are generated.
1 = MSI is generated.
Next Pointer: Pointer to the next item in the capabilities
list. Hardwired to 00h to indicate that MSI is the last item
in the Capabilities List.
Capability ID: Hardwired to 05h to indicate that the EDMA
Controller is MSI capable.
Bit Reset
Value
00h
0b
0h
001b
0b
00h
05h
Bit Access
RO
RW
RO
RW
RO
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
518
August 2009
Order Number: 320066-003US