EP80579 Datasheet, PDF (1477/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-50. RCTL: Receive Control Register (Sheet 4 of 4)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 0100h
Offset End: 0103h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 0100h
Offset End: 0103h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 0100h
Offset End: 0103h
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
07 : 06
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
LBM
LPE
MPE
UPE
SBP
EN
Rsvd
Loopback mode. These bits enable the loopback
function.When using a PHY, a value of 00 should be used
and the PHY is configured for loopback through the MDIO
interface.
• 00 = Normal operation (or PHY loopback in GMII/MII
mode)
• 01 = MAC Loopback enable (only supported for GMII/
MII mode)
• 10 = Reserved
• 11 = Reserved
• 11 = Reserved
Note: PHY devices require programming for loopback
operation using MDIO accesses.
Note: The GbE must be configured for Full-Duplex
operation if Mac Loopback mode is enabled.
Long packet enable. This bit controls whether long packet
reception is permitted.
0 = Disabled, hardware discards packets longer than
1522B
1 = Enabled, 16384B is the maximum packet size that the
GbE can receive
Multicast promiscuous enable.
0 = Disabled
1 = Enabled
Unicast promiscuous enable.
0 = Disabled
1 = Enabled
Store bad packets.
0 = Disabled
1 = Enabled
Receiver Enable.
0 = All incoming packets are immediately dropped and are
not stored in the receive FIFO. If a packet is already
in-progress when disabled it will be finished.
1 = Incoming packet reception is enabled.
Reserved
Bit Reset
Value
00h
0h
0h
0h
0h
0h
0h
Bit Access
RW
RW
RW
RW
RW
RW
RV
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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