EP80579 Datasheet, PDF (1267/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.8.1.4 Offset 06h: PCISTS – Device Status Register
Table 35-47. Offset 06h: PCISTS: PCI Device Status Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: M:3:0
Offset Start: 06h
Offset End: 07h
Size: 16 bit
Default: 0010h
Power Well: Core
Bit Range
15
14
13
12
11
10 : 09
08
07
06
05
04
03
02 : 00
Bit Acronym
Bit Description
Sticky
DPE
SSE
RMA
RTA
STA
DST
MDPE
FB2B
Reserved
MC66
CL
IS
Reserved
Detected Parity Error: The device does not implement
this functionality. The bit is hardwired to 0. The EP80579
uses signals for errors.
Signaled System Error: This bit is not implemented in
the GCU and is hardwired to 0.
Received Master Abort Status: This bit is not
implemented in the GCU and is hardwired to 0.
Received Target Abort Status: This bit is not
implemented in the GCU and is hardwired to 0.
Signaled Target Abort Status: This bit is not
implemented in the GCU and is hardwired to 0.
DEVSEL Timing: These bits are not implemented in the
GCU and is hardwired to 0.
Master Data Parity Error Detected: This bit is not
implemented in the GCU and is hardwired to 0. The
EP80579 uses signals for errors.
Fast Back-to-Back Capable: This bit is not implemented
in the GCU and is hardwired to 0.
Reserved
66 MHz Capable: This bit is not implemented in the GCU
and is hardwired to 0.
Capabilities List: This bit is hardwired to 1 to indicate
that the device has a capabilities list.
Interrupt Status: This bit is not implemented in the GCU
and is hardwired to 0. The GCU does not interrupt.
Reserved
Bit Reset
Value
0h
0h
0h
0h
0h
00b
0h
0h
0h
0h
1
0h
0h
Bit Access
RO
RO
RO
RO
RO
RO
RO
RO
RV
RO
RO
RO
RV
35.8.1.5
Offset 08h: RID – Revision ID Register
The value of this register comes from the ICH Compatibility Rev ID registers.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1267