EP80579 Datasheet, PDF (1164/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
32.3
Theory Of Operation
32.3.1
Timer Accuracy Rules
• The timers are expected to be accurate over any 1 ms period to within 0.05% of
the time specified in the timer resolution fields.
• Within any 100 microsecond period, the timer is permitted to report a time that is
up to two ticks too early or too late. Each tick must be less than or equal to 100 ns;
this represents an error of less than 0.2%.
• The timer must be monotonic. It must never return the same value on two
consecutive reads (unless the counter has rolled over and actually reached the
same value).
• The main counter is clocked by the 14.31818 MHz clock, synchronized into the
66.666 MHz domain. This results in a non-uniform duty cycle on the synchronized
clock, but does have the correct average period. The accuracy of the main counter
is as accurate as the 14.3818 MHz clock.
32.3.2
Interrupt Mapping
The interrupts associated with the various timers have several interrupt mapping
options. When reprogramming the HPET (High Precision Event Timer) interrupt routing
scheme (LEG_RT_CNF bit in the General Config Register), a spurious interrupt may
occur. This is because the other source of the interrupt (8254 timer) may be asserted.
Software must mask interrupts prior to clearing the LEG_RT_CNF bit.
Mapping Option 1: Legacy Replacement Option
In this case, the Legacy Rout bit (LEG_RT_CNF) is set. This forces the mapping found in
Table .
Table 32-8. Legacy Replacement Routing
Timer
0
1
2
8259 Mapping
IRQ0
IRQ8
As per IRQ Routing
Field
APIC Mapping
IRQ2
IRQ8
As per IRQ Routing
Field
Comment
In this case, the 8254 timer does not cause any
interrupts
In this case, the RTC does not cause any
interrupts.
Mapping Option 2: Standard Option
In this case, the Legacy Rout bit (LEG_RT_CNF) is zero. Each timer has its own routing
control. The interrupts can be routed to various interrupts in the I/O APIC. A
capabilities field indicates which interrupts are valid options for the routing.
If a timer is set for edge-triggered mode, the timers must not be shared with any PCI
interrupts.
Supported interrupt values are IRQ 20, 21, 22, and 23.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1164
August 2009
Order Number: 320066-003US