EP80579 Datasheet, PDF (1848/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 49-21. PCI Express* Differential Transmitter (TX) Specifications (Sheet 1 of 2)
Symbol
Parameter
Min
Nom
Max
Unit Figures Notes
V_TX-CM-DC- Tx Absolute Delta of DC Common
ACTIVE-IDLE- ^{Mode Voltage During L0 and}
0
-
100
mV
-
1
DELTA
Electrical Idle
V_TX-CM-DC- Tx Absolute Delta of DC Common
LINE-DELTA ^{Mode Voltage between D+ and D–}
0
-
25
mV
-
1
V_TX-DC-CM Tx DC Common Mode Voltage
0
-
3.6
V
-
2
I_TX-SHORT Tx Short Circuit Current Limit
-
90
mA
-
4
Z_TX-DIFF-DC Tx DC Differential Impedance
80
100
120 Ohms
-
Z_TX-DC
Tx DC impedance
40
-
-
Ohms
-
L_TX-SKEW Tx Lane-to-Lane Output Skew
-
-
500 ps
+ 2UI
-
3
C_TX
Tx AC Coupling Capacitor
V_O7
Tx Output Voltage
75
-
200
nF
-
6
800
-
1200
mVdiff
p-p
-
5
UI
Unit Interval
399.88 400 400.12 ps
-
7
V_TX-DIFFp-p
Differential Peak-to-Peak Output
Voltage
0.800
-
1.2
V
49-16
8
V_TX-DE-
RATIO
De-emphasized Differential Output
Voltage Ratio
–3.0
–3.5
–4.0
dB
49-16
8
T_TX-EYE Minimum Tx Eye Width
0.70
-
UI
49-16 8, 9
T_TX-EYE-
MEDIAN-to-
MAX-JITTER
Maximum time between the jitter
median and maximum deviation
from the median
-
-
0.15
UI
-
8, 9
T_TX-RISE,
T_TX-FALL
D+/D– Tx Output Rise/Fall time
0.125
-
-
UI
-
8, 11
V_TX-CM-ACp
AC Peak Common Mode Output
Voltage
-
20
mV
-
8
Notes:
1.
Specified at the measurement point into a timing and voltage compliance test load as shown in
Figure 49-14 and measured over any 250 consecutive Unit Intervals. Also refer to the Transmitter
Compliance Eye Diagram as shown in Figure 49-15.
2.
The allowed DC Common Mode voltage under any conditions. Refer to Section 4.3.1.8 in the PCI-
Express* Specification for further details.
3.
Static skew between any two Transmitter Lanes within a single link
4.
The allowed current when any output is shorted to ground.
5.
PCI-Express mVdiff p-p = PEx_Xp[x] - PEx_Xn[x]
6.
Guaranteed by design. These values are typical values seen for this process, but not measured during
production testing.
7.
No test load is necessarily associated with this value.
8.
Specified at the measurement point into a timing and voltage compliance test load as shown in
Figure 49-14 and measured over any 250 consecutive Unit Intervals. Also refer to the Transmitter
Compliance Eye Diagram as shown in Figure 49-16.
9.
A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-
JITTER-MAX = 0.30 UI for the transmitter collected over any 250 consecutive Tx UIs. The TTX-EYE-
MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the
maximum deviation from the median is less than half of the total Tx jitter budget collected over any
250 consecutive Tx UIs. Note that the median is not the same as the mean. The jitter median
describes the point in time where the number of jitter points on either side is approximately equal, as
opposed to the average value.
10.
The transmitter input impedance shall result in a differential return loss greater than or equal to 12
dB and a common mode return loss greater than 6 dB over a frequency range of 50 MHz to 1.25 GHz.
This input impedance requirement applies to all valid input levels. The reference impedance for return
less measurements is 50 Ω to ground for both the D+ and D– line (for example, as measured by a
Vector Network Analyzer with 50 Ω probes – see Figure 49-16). Note that the series capacitors CTX is
optional for the return loss measurement.
11.
Measured between 20–80% at Transmitter package pins into a test load as shown in Figure 49-16 for
both VTX-D+ and VTX-D–.
12.
Refer to Section 4.3.1.8 in the PCI-Express* Specification for further details.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1848
August 2009
Order Number: 320066-003US