EP80579 Datasheet, PDF (653/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-296.Bus 0, Device 1, Function 0: Summary of EDMA Configuration Registers
Mapped Through EDMALBAR Memory BAR (Sheet 2 of 2)
Offset Start Offset End
Register ID - Description
Default
Value
A8h
ACh
C0h
C4h
C8h
CCh
D0h
D4h
D8h
DCh
E0h
E4h
E8h
ECh
100h
104h
ABh
AFh
C3h
C7h
CBh
CFh
D3h
D7h
DBh
DFh
E3h
E7h
EBh
EFh
103h
107h
“Offset A8h: DCR2 - Channel 2Transfer Control Register” on page 672
00000000h
“Offset ACh: DCR2 - Channel 2 Descriptor Control Register” on page 672
00000000h
“Offset C0h: CCR3 - Channel 3 Channel Control Register” on page 673
00000000h
“Offset C4h: CSR3 - Channel 3 Channel Status Register” on page 673
00000000h
“Offset C8h: CDAR3 - Channel 3 Current Descriptor Address Register” on page 673 00000000h
“Offset CCh: CDUAR3 - Channel 3 Current Descriptor Upper Address Register” on
page 674
00000000h
“Offset D0h: SAR3 - Channel 3 Source Address Register” on page 674
00000000h
“Offset D4h: SUAR3 - Channel 3 Source Upper Address Register” on page 674
00000000h
“Offset D8h: DAR3 - Channel 3 Destination Address Register” on page 675
00000000h
“Offset DCh: DUAR3 - Channel 3 Destination Upper Address Register” on page 675 00000000h
“Offset E0h: NDAR3 - Channel 3 Next Descriptor Address Register” on page 675 00000000h
“Offset E4h: NDUAR3 - Channel 3 Next Descriptor Upper Address Register” on
page 676
00000000h
“Offset E8h: TCR3 - Channel 3 Transfer Count Register” on page 676
00000000h
“Offset ECh: DCR3 - Channel 3 Descriptor Control Register” on page 677
00000000h
“Offset 100h: DCGC - EDMA Controller Global Command” on page 677
00000000h
“Offset 104h: DCGS - EDMA Controller Global Status” on page 678
00000000h
16.6.1
16.6.1.1
Register Details
Offset 00h: CCR0 - Channel 0 Channel Control Register
The Channel Control Register (CCR) is cleared to zero on power-on or system reset.
The CCR specifies the overall operating environment for the channel. Software
initializes this register only after initializing the chain descriptors in system memory,
and the Next Address registers as pointer to the first chain descriptor in memory. CCR
can be written when the DMA channel is active. The CCR is a read/write register.
Table 16-297.Offset 00h: CCR0 - Channel 0 Channel Control Register (Sheet 1 of 3)
Description:
View: PCI
BAR: EDMALBAR
Bus:Device:Function: 0:1:0
Offset Start: 00h
Offset End: 03h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 04
Bit Acronym
Reserved Reserved
Bit Description
Sticky
Bit Reset
Value
000000h
Bit Access
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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