EP80579 Datasheet, PDF (1170/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Status bit preserved in RTC well for possible error detection and correction.
Drives WDT_TOUT# if OUTPUT is enabled.
• Timer can be disabled (default state) or Locked (Hard Reset required to disable
WDT).
• WDT Automatic Reload of Preload value when WDT Reload Sequence is performed.
33.3
33.3.1
Functional Description
Host Processor Interface (LPC)
The host processor communicates with the SIW via the LPC bus. Access is through a
series of read/ write registers and accomplished through I/O cycles. All registers are
eight bits wide. The SIW registers include global configuration space and device specific
regions accessed by setting the Logical Device Number in the SIW Configuration
Register 07H (SCR7).
Table 33-1. Address Map
Address
04Eh or 20Eh (SIU1_DTR#
dependent)
04Fh or 20Fh (SIU1_DTR#
dependent)
Base+(0-7)
Base+(0-7)
Base+(0-18)
Block Name
Configuration Index
Configuration Data
Serial Port 1
Serial Port 2
Watchdog Timer
Logical Device
04H
05H
06H
See Section 33.8 for configuration register descriptions and information on setting the
base address.
33.4
33.4.1
LPC Interface
The LPC interface is used to control all the logical blocks on the SIW. LPC bus signals
use PCI 33 MHz electrical signal characteristics. Refer to the Low Pin Count (LPC)
Interface Specification Rev 1.0.
LPC Cycles
The following cycle types are supported by the LPC protocol.
Table 33-2. Supported LPC Cycle Types
Cycle Type
I/O Write
I/O Read
Transfer Size
1 Byte
1 Byte
The SIW ignores cycles that it does not support.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1170
August 2009
Order Number: 320066-003US