EP80579 Datasheet, PDF (931/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
24.8.2
24.8.2.1
Register Details
Offset 09h: RSA: Receive Slave Address Register
Table 24-47. Offset 09h: RSA: Receive Slave Address Register
Description:
View: PCI
BAR: SM_BASE (IO)
Bus:Device:Function: 0:31:3
Offset Start: 09h
Offset End: 09h
Size: 8 bit
Default: 44h
Power Well: Resume
Bit Range
07
06 : 00
Bit Acronym
Bit Description
Sticky
Reserved
RSA
Reserved
SLAVE_ADDR[06:00]: This field is the slave address
that is decoded for read and write cycles. The default is
not 0 so that it can respond even before the processor
comes up (or if the processor is dead). This register is
reset by CF9 RESET or RSMRST#, but not by PLTRST#.
Bit Reset
Value
0b
1000100b
Bit Access
RW
24.8.2.2 Offset 0Ah: SD: Slave Data Register
Table 24-48. Offset 0Ah: SD: Slave Data Register
Description:
View: PCI
BAR: SM_BASE (IO)
Bus:Device:Function: 0:31:3
Offset Start: 0Ah
Offset End: 0Bh
Size: 16 bit
Default: 0000h
Power Well: Resume
Bit Range
15 : 00
Bit Acronym
Bit Description
Sticky
SLAVE_DATA[15:00]: This field is the 16-bit data
value written by the external SMBus master. The
processor can then read the value from this register.
This register is reset by CF9 RESET or RSMRST#, but
SD
not by PLTRST#. SLAVE_DATA[07:00] corresponds to
the Data Message Byte 0 (see Section 24.8.2.1) at
Slave Write Register 4 in the table. SLAVE_[15:08]
corresponds to the Data Message Byte 1 (see
Section 24.8.2.1) at Slave Write Register 5 in the table.
Bit Reset
Value
0h
Bit Access
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
931