EP80579 Datasheet, PDF (448/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.2.1.3
Offset 04h: PCICMD - PCI Command Register
Since IMCH Device 0 does not physically reside on PCI_A (internal bus) many of the
bits are not implemented.
Table 16-57. Offset 04h: PCICMD - PCI Command Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 04h
Offset End: 05h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 09
08
07 : 00
Bit Acronym
Bit Description
Sticky
Reserved
SERRE
Reserved
Reserved
SERR Enable: This bit is a global enable bit for Device 0
SERR messaging.
0 = Disable, SERR message is not generated by the IMCH
for Device 0, Function 1.
1 = The IMCH is enabled to generate SERR messages over
the NSI for specific Device 0, Function 1 error
conditions that are individually enabled in the
ERRCMD registers.
The IMCH communicates the SERR condition by sending a
DO_SERR message over NSI to the IICH. If this bit is set to
a 1, the IMCH is enabled to generate SERR messages over
NSI for specific Device 0, Function 1 error conditions that
are individually enabled in the NSI_SERRCMD,
FSB_SERRCMD, BUF_SERRCMD, and DRAM_SERRCMD
registers. The error status is reported in the PCISTS
register as well as the corresponding FERR/NERR registers.
Note: Reporting via SERR for detected parity error which
is essentially NSI Poisoned TLP’s, can ALSO be
reported through by the Device 0, Function 0.
Reserved
Bit Reset
Value
00h
0b
0b
Bit Access
RW
16.2.1.4
Offset 06h: PCISTS - PCI Status Register
PCISTS is a 16-bit status register that reports the occurrence of error events on Device
0’s PCI interface.
Table 16-58. Offset 06h: PCISTS - PCI Status Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 06h
Offset End: 07h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15
14
13 : 00
Bit Acronym
Bit Description
Sticky
Reserved
SSE
Reserved
Reserved
Signaled System Error:
0 = SERR is not generated by IMCH Device 0, Function 1
1 = IMCH Device 0 Function 1 generated a SERR message
over NSI for any enabled Device 0, Function 1 error
condition.
Software clears this bit by writing a 1 to the bit location.
Reserved
Bit Reset
Value
0b
0b
000h
Bit Access
RWC
Intel^® EP80579 Integrated Processor Product Line Datasheet
448
August 2009
Order Number: 320066-003US