EP80579 Datasheet, PDF (1125/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
30.2.2.9
ELCR1 - Master Edge/Level Control Register
In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In
level mode (bit[x] = 1), the interrupt is recognized by a high level. The cascade
channel, IRQ2, the heart beat timer (IRQ0), and the keyboard controller (IRQ1),
cannot be put into level mode.
Table 30-14. ELCR1 - Master Edge/Level Control Register
Description:
View: IA F
Base Address: 0000h (IO)
Offset Start: 4D0h
Offset End: 4D0h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07
06
05
04
03
02 : 00
Bit Acronym
Bit Description
Sticky
ECL7
ECL6
ECL5
ECL4
ECL3
Reserved
Edge Level Control IRQ7:
0 = Edge mode. The interrupt is recognized by a low to
high transition.
1 = Level mode. The interrupt is recognized by a high
level.
Edge Level Control IRQ6:
0 = Edge mode. The interrupt is recognized by a low to
high transition.
1 = Level mode. The interrupt is recognized by a high
level.
Edge Level Control IRQ5:
0 = Edge mode. The interrupt is recognized by a low to
high transition.
1 = Level mode. The interrupt is recognized by a high
level.
Edge Level Control IRQ4:
0 = Edge mode. The interrupt is recognized by a low to
high transition.
1 = Level mode. The interrupt is recognized by a high
level.
Edge Level Control IRQ3:
0 = Edge mode. The interrupt is recognized by a low to
high transition.
1 = Level mode. The interrupt is recognized by a high
level.
Reserved.
Bit Reset
Value
0h
0h
0h
0h
0h
0h
Bit Access
RW
RW
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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