EP80579 Datasheet, PDF (1163/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 32-7. Offset 108h: HPTCV[0-2] - Timer n Comparator Value Register
Description: Timer 0: 108 - 10Fh Timer 1: 128 - 12Fh Timer 2: 148 - 14Fh
View: IA F
Base Address: HPTC
Offset Start: 108h at 20h
Offset End: 10Fh at 20h
Size: 64 bit
Default: Xh
Power Well: Core
Bit Range
63 :00
Bit Acronym
Bit Description
Sticky
TIMn_COMP
Timer Compare Value:
Reads to this register return the current value of the
comparator.
Timers 0, 1, or 2 are configured to non-periodic mode:
Writes to this register load the value against which the
main counter must be compared for this timer.
• When the main counter equals the value last written
to this register, the corresponding interrupt can be
generated (if so enabled).
• The value in this register does not change based on
the interrupt being generated.
Timer 0 is configured to periodic mode:
• When the main counter equals the value last written
to this register, the corresponding interrupt can be
generated (if so enabled).
• After the main counter equals the value in this
register, the value in this register is increased by the
value last written to the register.
• For example, if the value written to the register is
00000123h, then:
1. An interrupt is generated when the main counter
reaches 00000123h.
2. The value in this register is then adjusted by the
hardware to 00000246h.
3. Another interrupt is generated when the main
counter reaches 00000246h.
4. The value in this register is then adjusted by the
hardware to 00000369h.
• As each periodic interrupt occurs, the value in this
register increments. When the incremented value is
greater than the maximum value possible for this
register (FFFFFFFFh for a 32-bit timer or
FFFFFFFFFFFFFFFFh for a 64-bit timer), the value
wraps around through zero. For example, if the
current value in a 32-bit timer is FFFF0000h and the
last value written to this register is 20000, then after
the next interrupt the value changes to 00010000h.
Default value for each timer is all 1s for the bits that are
implemented. For example, a 32-bit timer has a default
value of 00000000FFFFFFFFh. A 64-bit timer has a default
value of FFFFFFFFFFFFFFFFh.
Bit Reset
Value
Xh
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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